Thin film transistor, array substrate, and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11257955-B2
Application number	US-201816026307-A
Country	US
Kind code	B2
Filing date	Jul 3, 2018
Priority date	Sep 13, 2017
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.

First claim

The invention claimed is:

1. A method for fabricating a thin film transistor, the method comprising:
forming a gate, a gate insulation layer, and an active layer on an underlying substrate successively;
forming a patterned hydrophobic layer directly connected with the active layer, wherein the patterned hydrophobic layer comprises first pattern components, and orthographic projections of the first pattern components onto the underlying substrate completely overlap with an orthographic projection of a channel area at the active layer onto the underlying substrate; and
forming a source and a drain above the patterned hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer;
wherein the patterned hydrophobic layer further comprises second pattern components, orthographic projections of the second pattern components onto the underlying substrate completely overlap with orthographic projections of first areas at the active layer onto the underlying substrate, and the first areas are other areas on the two sides of the channel area than areas where the source and the drain are arranged;
wherein the forming the patterned hydrophobic layer directly connected with the active layer comprises:
forming a patterned photoresist layer with a first preset thickness above second areas of the active layer, wherein the pattern of the patterned photoresist layer is complementary to the pattern of the patterned hydrophobic layer, and the second areas are on the two sides of the channel area where the source and the drain are arranged;
forming a hydrophobic thin film with a second preset thickness above the patterned photoresist layer, wherein the second preset thickness is smaller than the first preset thickness; and
stripping away the patterned photoresist layer using photoresist stripping liquid, and also removing the hydrophobic thin film, above the patterned photoresist layer, in contact with the patterned photoresist layer, thus forming the patterned hydrophobic layer.

2. The method according to claim 1 , wherein the forming the patterned hydrophobic layer directly connected with the active layer comprises: forming the patterned hydrophobic layer of an all-fluorin polymer above the active layer.

3. The method according to claim 2 , wherein the forming the gate, the gate insulation layer, and the active layer on the underlying substrate successively comprises:
forming an aluminum/molybdenum metal thin film above the underlying substrate, and patterning the aluminum/molybdenum metal thin film into the gate;
forming a silicon dioxide thin film above the gate, and etching the silicon dioxide thin film into the gate insulation layer; and
forming an indium gallium zinc oxide thin film above the gate insulation layer, and patterning the indium gallium zinc oxide thin film into the active layer; and
the forming the source and the drain above the patterned hydrophobic layer comprises:

forming a molybdenum/aluminum/molybdenum metal thin film above the patterned hydrophobic layer, and patterning the molybdenum/aluminum/molybdenum metal thin film into the source and the drain.

4. The method according to claim 1 , wherein the forming the patterned hydrophobic layer directly connected with the active layer comprises: forming a patterned hydrophobic layer of Hexamethyl Disilazane (HMDS) above the active layer.

5. The method according to claim 4 , wherein the forming the gate, the gate insulation layer, and the active layer on the underlying substrate successively comprises:
forming a graphene thin film above the underlying substrate, and patterning the graphene thin film into the gate;
forming a Polyvinyl Pyrrolidone (PVP) thin film above the gate, and etching the PVP thin film into the gate insulation layer; and
forming a pentacene thin film above the gate insulation layer, and patterning the pentacene thin film into the active layer; and
the forming the source and the drain above the patterned hydrophobic layer comprises:

forming a graphene thin film above the patterned hydrophobic layer, and patterning the graphene thin film into the source and the drain.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Wang Qinghe
• Ding Luke
• Cheng Leilei
• Bao Jun
• Su Tongshang
• Wang Dongfang
• Yuan Guangcai

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P76/202 Primary

  for lift-off processes · CPC title

• H10P14/687

  the materials being fluorocarbon compounds, e.g. (CHxFy) n or polytetrafluoroethylene · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title