Eliminating yield impact of stochastics in lithography

US11257674B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11257674-B2
Application numberUS-202017008095-A
CountryUS
Kind codeB2
Filing dateAug 31, 2020
Priority dateMay 16, 2017
Publication dateFeb 22, 2022
Grant dateFeb 22, 2022

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  2. Abstract

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  5. First independent claim

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Abstract

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Methods and apparatuses for performing cycles of aspect ratio dependent deposition and aspect ratio independent etching on lithographically patterned substrates are described herein. Methods are suitable for reducing variation of feature depths and/or aspect ratios between features formed and partially formed by lithography, some partially formed features being partially formed due to stochastic effects. Methods and apparatuses are suitable for processing a substrate having a photoresist after extreme ultraviolet lithography. Some methods involve cycles of deposition by plasma enhanced chemical vapor deposition and directional etching by atomic layer etching.

First claim

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The invention claimed is: 1. A method of processing semiconductor substrates, the method comprising: providing a substrate having a patterned photoresist, the patterned photoresist comprising a first feature and a second feature, wherein the first feature is partially defined and comprises photoresist at a bottom of the first feature; after providing the substrate, preferentially depositing carbon-containing material on the photoresist such that more carbon-containing material is deposited at a bottom of the second feature than at the bottom of the first feature; and after depositing the carbon-containing material, performing atomic layer etching on exposed surfaces of the substrate. 2. The method of claim 1 , wherein the atomic layer etching is performed by: exposing the exposed surfaces of the substrate to an etching species and igniting a plasma while applying a bias to modify a surface of the exposed surfaces of the substrate and formed a modified surface, and exposing the modified surface to a second plasma for a duration sufficient to remove the modified surface. 3. The method of claim 2 , wherein a bias is applied when exposing the modified surface to the second plasma. 4. The method of claim 2 , wherein the modified surfaces are etched without sputtering material underlying the modified surface. 5. The method of claim 2 , wherein exposing the exposed surfaces of the substrate to the etching species further comprises introducing a diluent inert gas selected from the group consisting of helium, argon, neon, krypton, and xenon. 6. The method of claim 1 , wherein the substrate further comprises an underlayer adjacent to, and underlying the photoresist, and the carbon-containing material is preferentially deposited so as not to deposit on exposed regions of the underlayer. 7. The method of claim 1 , wherein the carbon-containing material selectively deposited on the photoresist has a slower etch rate than the photoresist when exposed to the atomic layer etching. 8. The method of claim 1 , wherein etch rate of the photoresist during atomic layer etching is faster than etch rate of the carbon-containing material. 9. The method of claim 1 , wherein the atomic layer etching removes photoresist anisotropic ally. 10. The method of claim 1 , wherein deposition thickness in the first and second features is dependent on aspect ratio of the first and second features. 11. The method of claim 1 , wherein the photoresist is patterned by deep ultraviolet lithography. 12. The method of claim 1 , wherein the photoresist is patterned by extreme ultraviolet lithography. 13. The method of claim 1 , wherein the photoresist is patterned by immersion lithography. 14. The method of claim 13 , wherein the immersion lithography involves exposing the photoresist to argon fluoride. 15. The method of claim 1 , wherein preferentially depositing the carbon-containing material on the photoresist on the substrate further comprises introducing methane. 16. The method of claim 1 , wherein preferentially depositing and performing atomic layer etching are repeated in cycles until the first feature has the same critical dimension as the second feature. 17. A method of processing semiconductor substrates, the method comprising: providing a substrate having a patterned photoresist, the patterned photoresist comprising a first feature and a second feature, wherein feature depth of the first feature is less than thickness of the patterned photoresist; after providing the substrate, depositing carbon-containing material over the patterned photoresist by plasma enhanced chemical vapor deposition; and after depositing the carbon-containing material, etching the substrate by modifying a surface of exposed surfaces on the substrate to form modified surfaces and etching the modified surfaces. 18. The method of claim 17 , further comprising prior to providing the substrate, forming the patterned photoresist by extreme ultraviolet lithography. 19. The method of claim 17 , further comprising repeating the depositing and the etching in cycles such that each cycle causes the feature depth of the first feature to approach the thickness of the patterned photoresist.

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Classifications

  • by chemical means · CPC title

  • of materials not containing Si, e.g. PZT or Al2O3 · CPC title

  • composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

  • in the presence of a plasma [PECVD] · CPC title

  • characterised by the processes involved to create the masks · CPC title

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What does patent US11257674B2 cover?
Methods and apparatuses for performing cycles of aspect ratio dependent deposition and aspect ratio independent etching on lithographically patterned substrates are described herein. Methods are suitable for reducing variation of feature depths and/or aspect ratios between features formed and partially formed by lithography, some partially formed features being partially formed due to stochasti…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P76/4088. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 22 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).