Formal verification tool to verify hardware design of memory unit

Patent metadata

Field	Value
Publication number	US-11250927-B2
Application number	US-202016792582-A
Country	US
Kind code	B2
Filing date	Feb 17, 2020
Priority date	Nov 11, 2015
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

First claim

What is claimed is:

1. A formal verification tool configured to verify operation of an instantiation of a hardware unit for storing data defined in a hardware design, the formal verification tool comprising:
monitoring logic configured to monitor one or more control signals of the instantiation of the hardware unit to detect writes to a symbolic address of the instantiation of the hardware unit and reads of the symbolic address of the instantiation of the hardware unit, wherein the symbolic address is a variable that represents each possible address value of the instantiation of the hardware unit which causes the formal verification tool to assess each of the possible address values; and
assertion verification logic configured to verify a formal assertion that establishes that when the monitoring logic detects a read of the symbolic address that occurs after one or more writes to the symbolic address, read data corresponding to the read of the symbolic address matches write data corresponding to the one or more writes to the symbolic address.

2. The formal verification tool of claim 1 , further comprising a seen symbolic write register and wherein the monitoring logic is further configured to, in response to detecting a write to the symbolic address, determine if write data corresponding to the write to the symbolic address matches symbolic data, and in response to determining the write data matches the symbolic data, set the seen symbolic write register.

3. The formal verification tool of claim 2 , further comprising a symbolic read request register and wherein the monitoring logic is further configured to, in response to detecting a read of the symbolic address when the seen symbolic write register is set, set the symbolic read request register; and
wherein the assertion verification logic is configured to verify the formal assertion by, in response to determining the seen symbolic write register is set and the symbolic read request register is set, comparing the read data corresponding to the read of the symbolic address to the symbolic data.

4. The formal verification tool of claim 3 , wherein the assertion verification logic is further configured to output an error message in response to determining that the read data corresponding to the read of the symbolic address does not match the symbolic data.

5. The formal verification tool of claim 3 , further comprising a symbolic mask register, and wherein the monitoring logic is configured to, in response to detecting a write of the symbolic data to the symbolic address, record in the symbolic mask register which particular bits of a memory block were written to; and
wherein the assertion verification logic is configured to combine each of the read data corresponding to the read of the symbolic address and the symbolic data with the data in the symbolic mask register prior to comparing the read data corresponding to the read of the symbolic address and the symbolic data.

6. The formal verification tool of claim 1 , further comprising:
a symbolic read request register, and wherein the monitoring logic is further configured to, in response to detecting a read of the symbolic address, set the symbolic read request register; and
a last written data register, and wherein the monitoring logic is further configured to, in response to detecting a write to the symbolic address, store write data corresponding to the write to the symbolic address in the last written data register.

7. The formal verification tool of claim 6 , wherein the assertion verification logic is configured to verify the formal assertion by, in response to determining the symbolic read request register is set, comparing the read data corresponding to the read of the symbolic address to the write data in the last written data register.

8. The formal verification tool of claim 7 , wherein the assertion verification logic is configured to output an error message in response to determining that the read data corresponding to the read of the symbolic address does not match the write data in the last written data register.

9. The formal verification tool of claim 7 , further comprising an initialized register, and wherein the monitoring logic is configured to, in response to detecting a write to the symbolic address, update the initialized register to indicate which particular bits of a memory block at the symbolic address have been written to at least once.

10. The formal verification tool of claim 9 , wherein the assertion verification logic is configured to combine each of the read data corresponding to the read of the symbolic address and the write data in the last written data register with the data in the initialized register prior to comparing the read data corresponding to the read of the symbolic address and the write data in the last written data register.

11. The formal verification tool of claim 3 , further comprising a seen symbolic read register, and wherein the monitoring logic is further configured to, monitor the one or more control signals to detect that read data corresponding to the read of the symbolic address has been output, and in response to detecting that read data corresponding to the read of the symbolic address has been output, set the seen symbolic read register.

12. The formal verification tool of claim 11 , wherein the assertion verification logic is further configured to perform the comparison only if the seen symbolic read register is set.

13. The formal verification tool of claim 1 , wherein the hardware unit implements one or more of: multiple access ports, partial reads and writes, pipelining, and clock gating.

14. A test system configured to verify a hardware design for a hardware unit for storing data, the test system comprising:
the formal verification tool as set forth in claim 1 ; and
a configuration application program interface configured to identify the one or more control signals of the hardware unit to be monitored by the monitoring logic based on a type of the hardware unit, a configuration of the hardware unit or both the type of the hardware unit and the configuration of the hardware unit.

15. A method of verifying operation of an instantiation of a hardware unit for storing data defined by a hardware design, the method comprising:
monitoring, using a formal verification tool, one or more control signals of the instantiation of the hardware unit to detect writes to a symbolic address of the instantiation of the hardware unit, wherein the symbolic address is a variable that represents each possible address value of the instantiation of the hardware unit which causes a formal verification tool to assess each of the possible address values;
monitoring, using the formal verification tool, one or more control signals of the instantiation of the hardware unit to detect reads of the symbolic address of the instantiation of the hardware unit; and
verifying operation of the instantiation of the hardware unit, using the formal verification tool, by verifying a formal assertion that establishes that when a read of the symbolic address occurs after one or more writes to the symbolic address, read data corresponding to the read of the symbolic address matches write data corresponding to the one or more writes to the symbolic address.

16. The method of claim 15 , further comprising in response to detecting a write to the symbolic address, storing write data corresponding to the write to the symbolic address in a last written data register; and wherein verifying the formal assertion comprises comparing the read data corresponding to the read of the symbolic ad

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish
• Singleton Iain

Classifications

• G06F11/2221 Primary

  to test input/output devices or peripheral units · CPC title

• G11C8/00

  Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413) · CPC title

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G11C2029/0409

  Online test · CPC title