Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling

Patent metadata

Field	Value
Publication number	US-11249536-B2
Application number	US-201816222381-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Dec 17, 2018
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.

First claim

What is claimed is:

1. A method of scaling a frequency of an interface, comprising:
sending a command, via a serial interface operating at a first clock frequency, to a device for execution by the device;
operating the serial interface at a second clock frequency in response to sending the command;
operating the serial interface at the first clock frequency in response to determining the device is ready for another command;
incrementing a counter value to track an execution time of the command;
comparing the counter value to an operation value determined from a previous command execution time; and
based on the comparison, polling the device for a status; and
operating the serial interface at the first clock frequency in response to the status indicating that the device is ready for another command.

2. The method of claim 1 , wherein:
sending the command comprises sending the command via a serial peripheral interface (SPI) or a Quad SPI (QSPI) to a memory device.

3. The method of claim 1 , wherein:
sending the command to the device comprises sending the command to a NAND FLASH memory device or a NOR FLASH memory device.

4. The method of claim 1 , wherein:
sending the command to the device comprises sending one of a read command, a write command, an erase command, and a reset command; and
operating the serial interface at the second clock frequency comprises operating the serial interface at a clock frequency that is lower than the first clock frequency.

5. The method of claim 4 , wherein:
the second clock frequency is less than 3/20 of the first clock frequency.

6. An interface controller, comprising:
a serial interface configured to couple to a wire-based communication link; and
a control system coupled to the serial interface, the control system configured to:
operate the serial interface at a first clock frequency to send a command via the wire-based communication link to a device for execution by the device;
operate the serial interface at a second clock frequency in response to the command being sent;
increment a counter value to track an execution time of the command;
compare the counter value to an operation value determined from a previous command execution time;
based on the comparison, polling the device for a status; and
operate the serial interface at the first clock frequency in response to the status indicating that the device is ready for another command.

7. The interface controller of claim 6 , wherein the serial interface comprises a serial peripheral interface (SPI) or a Quad SPI (QSPI) and the device comprises a memory device.

8. The interface controller of claim 6 , wherein the device comprises a NAND FLASH memory device or a NOR FLASH memory device.

9. The interface controller of claim 6 , wherein:
the command comprises one of a read command, a write command, an erase command, and a reset command; and
the second clock frequency is lower than the first clock frequency.

10. The interface controller of claim 9 , wherein the second clock frequency is less than 3/20 of the first clock frequency.

Assignees

• Qualcomm Inc

Inventors

• Kumar Sandeep
• Kumar Suman
• Balani Deven

Classifications

• G06F13/4291

  using a clocked protocol · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/4247 Primary

  on a daisy chain bus · CPC title