Frequency detector for clock data recovery

Patent metadata

Field	Value
Publication number	US-11245554-B1
Application number	US-202016903377-A
Country	US
Kind code	B1
Filing date	Jun 17, 2020
Priority date	Jun 17, 2020
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

First claim

What is claimed is:

1. A method of clock and data recovery (CDR), comprising:
generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal;
receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate an FD output;
multiplying the FD output by a user-defined FD gain;
adding the FD output, as multiplied by the FD gain, to a phase detector (PD) output and a delayed PD output in a frequency path of the CDR unit; and
multiplying a sum comprising FD output, the PD output, and the delayed PD output by a frequency path gain in the frequency path of the CDR.

2. The method of claim 1 , wherein the first error signal includes a next data term with one of a decision feedback equalizer (DFE) or a feed forward equalizer (FFE) coefficient, and the at least one additional error signal respectively includes the same term with a modification of the DFE or FFE coefficient.

3. The method of claim 2 , wherein the first error signal includes a DFE coefficient, and wherein the at least one additional error signal includes a first additional error signal and a second additional error signal.

4. The method of claim 2 , wherein the first error signal includes an FFE coefficient, and wherein the at least one additional error signal includes a first additional error signal and a second additional error signal.

5. The method of claim 1 , wherein the FD output represents whether a local sampling clock is too fast, or too slow, relative to an incoming data stream.

6. The method of claim 5 , wherein the FD output is:
a negative number when the first error signal, and the at least two additional error signals all change from being >0 to being <0;
a positive number when the first error signal, and the at least two additional error signals all change from being <0 to being >0; and
zero, otherwise.

7. The method of claim 1 , further comprising:
detecting that a local sampling clock has locked onto a frequency of an incoming data stream; and
in response to the detection, set the FD output at 0.

8. A method of clock and data recovery (CDR), comprising:
generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal;
receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate an FD output;
multiplying the FD output by a user-defined FD gain;
adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit, wherein the first error signal includes a next data term with one of a decision feedback equalizer (DFE) or a feed forward equalizer (FFE) coefficient, and the at least one additional error signal respectively includes the same term with a modification of the DFE or FFE coefficient, wherein the first error signal includes a DFE coefficient, and wherein the at least one additional error signal includes a first additional error signal and a second additional error signal, and wherein:
the first error signal is expressed as: e k =sign[y k −d k+1 *(h 1 )−d k *h 0 ];
the first additional error signal is expressed as: e ke =sign[y k −d k+1 *(h 1+ h 1e0 )−d k *h 0 ]; and
the second additional error signal is expressed as: e kl =sign[y k −d k+1 *(h 1+ h 1l0 )−d k *h 0 ],
wherein y k is a kth received signal, d k+1 is a (k+1)th recovered data,

h 0 is a main cursor, h1 is the DFE coefficient, and h 1e0 and h 1l0 are an early offset and a late offset, relative to h1, respectively.

9. A method of clock and data recovery (CDR), comprising:
generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal;
receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate an FD output;
multiplying the FD output by a user-defined FD gain;

adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit, wherein the first error signal includes an FFE coefficient, and wherein the at least one additional error signal includes a first additional error signal and a second additional error signal, wherein:
the first error signal is expressed as: e k =sign[y k +y k+1 *(f 1 )−d k *h 0 ];
the first additional error signal is expressed as: e ke =sign[y k +y k+1 *(f 1+ f 1e0 )−d k *h 0 ]; and
the second additional error signal is expressed as: e kl =sign[y k +y k+1 *(f 1+ f 1l0 )−d k *h 0 ;
wherein y k is a (k)th received signal and y k+1 is a (k+1)th received signal, d k is a (k)th recovered data, h 0 is a main cursor, f 1 is an FFE coefficient,

and
f 1e0 and f 1l0 are an early offset and a late offset, relative to the FFE coefficient f 1 , respectively.

10. A CDR circuit, comprising:
a set of slicers configured to receive a serial data stream and generate a data signal d k , a first error signal e k and at least one additional error signal;
a phase detector (PD) configured to produce a PD output, the PD coupled to the set of slicers, the PD including an input configured to receive d k and e k and an output coupled to a phase path and a frequency path;
a frequency detector (FD) configured to produce an FD output, the FD coupled to the set of slicers and to a multiplier, configured to receive d k , e k , and the at least one additional error signal from the set of slicers, and to output a frequency vote to the multiplier;
a multiplier, coupled to the FD, configured to multiply the frequency vote by a pre-determined frequency detector gain, and output a frequency vote product to the frequency path;
an adder and a delay disposed in the frequency path, wherein the delay is configured to produce a delayed PD output, and the adder is configured to add the PD output, the delayed PD output, and the FD output.

11. The CDR circuit of claim 10 , wherein the frequency path includes a summer that adds an output of the PD, a delayed version of the output of the PD, and the frequency vote product.

12. The CDR circuit of claim 10 , further comprising an equalizer integrated with the set of slicers.

13. The CDR circuit of claim 10 , further comprising a lock detector, coupled to the FD and to the multiplier, configured to:
determine that a local sampling clock has locked onto a frequency of an incoming data stream; and
in response to the determination, set an FD frequency vote to equal 0, or shut off the FD.

14. The CDR circuit of claim 10 , wherein the frequency vote is:
a negative number when the first error signal, and the at least two additional error signals all change from being >0 to being <0;
a positive number when the first error signal, and the at least two additional error signals all change from being <0 to being >0; and
zero, otherwise.

15. The CDR circuit of claim 10 , wherein the frequency vote represents whether a local sampling clock is too fast, or too slow, relative to an incoming data stream.

16. A CDR circuit, comprising:
a set of slicers configured to receive a serial data stream and generate a data signal d k , a first error signal e k and at least one additional error signal;
an equalizer integrated with the set of slicers;
a phase detector (PD) coupled to the set of slicers, the PD including an input configured to receiv

Assignees

• Xilinx Inc

Inventors

• Zhang Hongtao
• Lin Winson
• Roldan Arianne
• Frans Yohan
• Zhang Geoff

Classifications

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L25/4917

  using multilevel codes · CPC title