Vertical multi-gate thin film transistors

Patent metadata

Field	Value
Publication number	US-11245038-B2
Application number	US-201716490503-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Mar 30, 2017
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

First claim

What is claimed is:

1. A vertical thin film transistor, comprising:
a gate electrode extending from an underlying material;
a gate dielectric over a sidewall of the gate electrode;
a semiconductor layer over the gate dielectric, the semiconductor layer separated from the sidewall of the gate electrode by at least the gate dielectric;
one or more isolation dielectric materials surrounding the semiconductor layer;
a first contact metallization in contact with a first portion of the semiconductor layer; and
a second contact metallization in contact with a second portion of the semiconductor layer.

2. The transistor of claim 1 , wherein:
the gate dielectric comprises a cladding surrounding the gate electrode;
the semiconductor layer comprises a cladding surrounding the gate dielectric;
the one or more isolation dielectric materials comprise a cladding surrounding the semiconductor layer; and
a portion of the semiconductor layer between the gate dielectric and the isolation dielectric materials separates the first contact metallization from the second contact metallization.

3. The transistor of claim 1 , wherein:
the semiconductor layer comprises an oxide;
the gate dielectric comprises a metal oxide; and
the one or more isolation dielectric materials comprise at least a first dielectric and a second dielectric surrounding the first dielectric.

4. The transistor of claim 3 , wherein:
the first contact metallization is within a first trench in at least the first dielectric layer, a wall of the first trench comprising the second dielectric; and
the second contact metallization is within a second trench in at least the first dielectric layer, a wall of the second trench comprising the second dielectric.

5. The transistor of claim 4 , wherein:
the first dielectric is separated from the semiconductor layer by one or more intervening dielectric layers;
the first trench is in the first dielectric layer and the one or more intervening dielectric layers; and
the second trench is in the first dielectric layer and the one or more intervening dielectric layers.

6. The transistor of claim 1 , wherein:
the gate electrode has a first height from the underlying material;
the first and second contact metallizations are in contact with the semiconductor layer along a top portion of the first height; and
the isolation dielectric materials are in contact with the semiconductor layer along a bottom portion of the first height, between the top portion and the underlying material.

7. The transistor of claim 6 , wherein:
a top surface of the semiconductor layer is recessed below a top surface of the first and second contact metallizations;
the gate electrode has a first height from the underlying material; and
the first and second contact metallizations have a second height, less than the first height.

8. The transistor of claim 7 , wherein the semiconductor layer is separated from the underlying material by the gate dielectric.

9. The transistor of claim 1 , further comprising:
a second gate electrode extending from the underlying material; and
wherein:
the gate dielectric comprises a first cladding surrounding the gate electrode and a second cladding surrounding the second gate electrode;
the semiconductor layer surrounds the first cladding and the second cladding;
the one or more dielectric materials comprise a cladding surrounding the semiconductor layer; and
a first portion of the semiconductor layer between the first and second gate electrodes separates the first contact metallization from the second contact metallization.

10. The transistor of claim 9 , wherein a longitudinal length of at least one of the contact metallizations is at least equal to that of the first gate electrode summed with that of the second gate electrode.

11. A computer platform including:
a processor; and
a memory device coupled to the processor, wherein at least one of the processor and memory device comprises the thin film transistor recited in claim 1 .

12. An integrated circuit memory device, comprising:
a memory cell array including a plurality of thin film transistors (TFTs), wherein individual ones of the TFTs comprise:
a gate electrode extending from an underlying material surface;
a gate dielectric over a sidewall of the gate electrode;
a semiconductor layer over the gate dielectric, the semiconductor layer separated from the sidewall of the gate electrode by at least the gate dielectric;
one or more isolation dielectric materials surrounding the semiconductor layer;
a first contact metallization in contact with a first portion of the semiconductor layer; and
a second contact metallization in contact with a second portion of the semiconductor layer.

13. The memory device of claim 12 , wherein the underlying material surface further comprises an inter-level dielectric (ILD) layer that is over a substrate, the substrate including a plurality of metal-oxide-semiconductor field effect transistors (MOSFETs) comprising a monocrystalline semiconductor material.

14. The memory device of claim 13 , wherein at least the gate electrode is electrically coupled to one of the MOSFETs through a wordline.

15. A method of fabricating a thin film transistor (TFT), the method comprising:
forming a gate pillar extending from an underlying material, the gate pillar comprising a gate dielectric on a sidewall of a gate electrode material;
forming a semiconductor layer over a sidewall of the gate pillar, the semiconductor layer covering the gate dielectric on the sidewall of the gate pillar;
forming one or more dielectric materials around the gate pillar;
forming a pair of openings in the dielectric materials, each opening exposing a portion of the semiconductor layer; and
forming contact metallization within the openings.

16. The method of claim 15 , wherein forming the gate pillar comprises:
patterning a feature into a sacrificial material layer;
backfilling the feature with the gate electrode material;
removing the sacrificial material layer to expose the sidewall of the gate electrode material; and
depositing the gate dielectric over the exposed sidewall of the gate electrode material.

17. The method of claim 16 , wherein forming the gate pillar comprises:
recessing a top surface of the gate electrode material from a top surface of the sacrificial material layer; and
forming a dielectric cap over the recessed top surface of the gate electrode material, wherein the dielectric cap has a composition distinct from that of the sacrificial material layer.

18. The method of claim 15 , wherein forming the semiconductor layer comprises depositing a semiconductor material comprising oxygen.

19. The method of claim 18 , wherein forming the semiconductor layer comprises:
blanket depositing the semiconductor layer over the gate pillar and the underlying material; and
removing the semiconductor layer from at least a portion of the underlying material adjacent to the gate pillar.

20. The method of claim 19 , wherein removing the semiconductor layer from the underlying material further comprises:
depositing a spacer dielectric over the semiconductor layer;
anisotropically etching the spacer dielectric to form a dielectric spacer protecting the semiconductor layer covering the gate dielectric material on the sidewall; and
removing the semiconductor layer unprotected by the dielectric spacer.

21. The method of claim 20 , wherein:
forming one or more dielectric materials around

Assignees

• Intel Corp

Inventors

• Wang Yih
• Sharma Abhishek
• Ma Sean
• Lee Van H

Classifications

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6728 Primary

  Vertical TFTs · CPC title