Thin film transistor, method for preparing the same, array substrate, display panel and apparatus

Patent metadata

Field	Value
Publication number	US-11245015-B2
Application number	US-202016937700-A
Country	US
Kind code	B2
Filing date	Jul 24, 2020
Priority date	Aug 22, 2019
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

The present disclosure relates to the field of display technologies, and discloses a Thin Film Transistor, a method for preparing the same, an array substrate, a display panel and an apparatus. The TFT includes: a base substrate; an active layer; a source electrode; and a drain electrode; where the active layer, the source electrode, and the drain electrode are sequentially laminated on the base substrate; and a projection of the source electrode on the base substrate covers a projection of part of edges of the active layer on the base substrate.

First claim

What is claimed is:

1. A Thin Film Transistor (TFT), comprising:
a base substrate;
an active layer;
a source electrode; and
a drain electrode;
wherein the active layer, the source electrode, and the drain electrode are sequentially laminated on the base substrate; and
a projection of the source electrode on the base substrate covers a projection of part of edges of the active layer on the base substrate;
wherein the source electrode coats the part of the edges of the active layer;
wherein the source electrode is U-shaped, the active layer is a square shape, the part of the edges of the active layer comprises three edges, and the source electrode coats the three edges of the active layer; wherein projections of two end faces of the source electrode on the base substrate partially coincide with a projection of an edge, other than the three edges, of the active layer on the base substrate; or
the source electrode is L-shaped, the active layer is a square shape, the part of the edges of the active layer comprises two edges, the source electrode coats the two edges of the active layer, and the two edges of the active layer are adjacent.

2. The TFT according to claim 1 , wherein the drain electrode is a strip shape, and
one end of the drain electrode is inserted in a region surrounded by the source electrode.

3. The TFT according to claim 1 , wherein the active layer comprises a semiconductor layer and an ohmic contact layer which are sequentially laminated;
a pattern of the ohmic contact layer is similar to a pattern of the source and drain electrodes;
a channel region is formed between the source electrode and the drain electrode; and
a projection of an edge of a side, facing the channel region, of the ohmic contact layer on the base substrate at least partially coincides with a projection of an edge of a side, facing the channel region, of the source and drain electrodes on the base substrate.

4. An array substrate, comprising the TFT according to claim 1 .

5. A display panel, comprising the array substrate according to claim 4 .

6. A display apparatus, comprising the display panel according to claim 5 .

7. The display apparatus according to claim 6 , wherein the display apparatus is a vehicle-mounted display apparatus.

8. A method for preparing the TFT according to claim 1 , comprising:
forming the active layer on a base substrate;
preparing a metal layer on the active layer; and
forming a pattern of source and drain electrodes by a patterning process.

9. The method according to claim 8 , wherein the forming the active layer on the base substrate comprises:
preparing a semiconductor layer and an ohmic contact layer on the base substrate sequentially; and
forming a pattern of the ohmic contact layer by the patterning process;
wherein the pattern of the ohmic contact layer is similar to the pattern of the source and drain electrodes,
a channel region is formed between the source electrode and the drain electrode of the source and drain electrodes, and
a projection of an edge of a side, facing the channel region, of the ohmic contact layer on the base substrate at least partially coincides with a projection of an edge of a side, facing the channel region, of the source and drain electrodes on the base substrate.

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Chen Chuan
• Chen Pengyu
• Ma Tao
• Yang Chengshao

Classifications

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D64/259

  Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric · CPC title

• H10D30/6723

  having light shields · CPC title