TFT and manufacturing method thereof, array substrate

Patent metadata

Field	Value
Publication number	US-9620652-B2
Application number	US-201414500243-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Mar 26, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

The present invention provides a TFT and a manufacturing method thereof, an array substrate and a display device. The TFT comprises a gate, an active layer located on the gate, an ohmic contact layer located on the active layer, and a first electrode and a second electrode located on the ohmic contact layer, wherein the first electrode and the second electrode are partially overlapped with the active layer, the ohmic contact layer is located within a region where the first electrode and the second electrode are overlapped with the active layer; the active layer is partially overlapped with the gate, the active layer comprises at least one opening region partially overlapped with the gate; and the first electrode and/or the second electrode extends beyond the active layer through the at least one opening region.

First claim

The invention claimed is:

1. A thin film transistor, comprising a gate, an active layer located on the gate, an ohmic contact layer located on the active layer, and a first electrode and a second electrode located on the ohmic contact layer, wherein the first electrode and the second electrode are partially overlapped with the active layer, and the ohmic contact layer is located within a region where the first electrode and the second electrode are overlapped with the active layer, wherein,
the active layer is partially overlapped with the gate, and the active layer comprises at least one opening region which is partially overlapped with the gate and wherein the at least one opening region is provided inside the active layer so that the active: layer forms a closed loop; and
the first electrode and/or the second electrode extends beyond the active layer through the at least one opening region, and is overlapped with the active layer outside the gate.

2. The thin film transistor according to claim 1 , wherein the first electrode is a source and the second electrode is a drain; or, the first electrode is a drain and the second electrode is a source.

3. The thin film transistor according to claim 1 , further comprising a gate insulating layer located between the gate and the active layer to cover the gate.

4. The thin film transistor according to claim 1 , wherein the active layer comprises two opening regions; and
the first electrode extends beyond the active layer through one of the two opening regions, and the second electrode extends beyond the active layer through the other opening region.

5. The thin film transistor according to claim 4 , wherein the two opening regions are located on two opposite sides of the gate respectively.

6. The thin film transistor according to claim 5 , wherein the openings of the active layer are formed horizontally opposite one another; and
the active layer has a pattern of a Chinese character “ ”.

7. The thin film transistor according to claim 5 , wherein the openings of the active layer are formed vertically opposite one another; and
the active layer has a pattern of a transversely-placed Chinese character “ ”.

8. The thin film transistor according to claim 4 , wherein the two opening regions are located on two adjacent sides of the gate respectively.

9. The thin film transistor according to claim 5 , wherein the active layer further comprises an opening region located on one side between the two opposite sides of the gate.

10. The thin film transistor according to claim 4 , wherein the opening regions are rectangular, circular or elliptical in shape.

11. The thin film transistor according to claim 8 , wherein the opening regions are rectangular, circular or elliptical in shape.

12. The thin film transistor according to claim 1 , wherein the size of an overlapping region in the active layer is determined according to the number of holes generated in a part of the active layer which is overlapped with the gate when a negative bias is applied to the gate, and the orthographic projection of the overlapping region is located outside the gate and the overlapping region is overlapped with the first electrode and/or the second electrode.

13. The thin film transistor according to claim 1 , wherein the ohmic contact layer is made of N-doped amorphous silicon and the active layer is made of amorphous silicon.

14. An array substrate, comprising the thin film transistor according to claim 1 .

15. The array substrate according to claim 14 , wherein the active layer comprises two opening regions; and
the first electrode extends beyond the active layer through one of the two opening regions, and the second electrode extends beyond the active layer through the other opening region.

16. The array substrate according to claim 15 , wherein the two opening regions are located on two opposite sides of the gate respectively.

17. The array substrate according to claim 15 , wherein the two opening regions are located on two adjacent sides of the gate respectively.

18. A method for manufacturing a thin film transistor, comprising the following steps of:
forming a gate on a base substrate;
forming an active layer on the gate;
forming an ohmic contact layer on the active layer; and
forming a first electrode and a second electrode on the ohmic contact layer so that the first electrode and the second electrode are partially overlapped with the active layer, and the ohmic contact layer is located within a region where the first electrode and the second electrode are overlapped with the active layer,
wherein the active layer is partially overlapped with the gate, and the active layer comprises at least one opening region which is partially overlapped with the gate and wherein the at least one opening region is provided inside the active layer so that the active layer forms a closed loop; and the first electrode and/or the second electrode extends beyond the active layer through the at least one opening region, and is overlapped with the active layer outside the gate.

19. The method for manufacturing a thin film transistor according to claim 18 , further comprising a step of forming a gate insulating layer on the gate to cover the gate between the step of forming a gate on the base substrate and the step of forming an active layer on the gate.

20. The method for manufacturing a thin film transistor according to claim 18 , wherein the active layer comprises two opening regions; and
the first electrode extends beyond the active layer through one of the two opening regions, and the second electrode extends beyond the active layer through the other opening region.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Shen Qiyu

Classifications

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/78696 Primary

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic

• H10D30/6729

  characterised by the electrodes · CPC title