Thin film transistor, method for manufacturing the same, array substrate and display device

Patent metadata

Field	Value
Publication number	US-10504940-B2
Application number	US-201715820121-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Apr 25, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A thin film transistor comprises a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode. The drain electrode comprises a first sub-drain electrode and at least one second sub-drain electrode. A first portion of the active layer between the first sub-drain electrode and the source electrode and a second portion of the active layer between each of the at least one second sub-drain electrode and the source electrode are used for forming different portions of a primary channel, respectively. The first sub-drain electrode is a signal input electrode, and a third portion of the active layer between the first sub-drain electrode and each of the at least one second sub-drain electrode is used for forming an auxiliary channel. A channel length of the auxiliary channel is less than or equal to a channel length of the primary channel.

First claim

What is claimed is:

1. A thin film transistor, comprising a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein,
the drain electrode comprises a first sub-drain electrode and at least one second sub-drain electrode that are physically detached from one another, and a first portion of the active layer between the first sub-drain electrode and the source electrode, and a second portion of the active layer between each of the at least one second sub-drain electrode and the source electrode are used for forming different portions of a primary channel, respectively;
the first sub-drain electrode is a signal input electrode, and a third portion of the active layer between the first sub-drain electrode and each of the at least one second sub-drain electrode is used for forming an auxiliary channel, a channel length of the auxiliary channel being less than or equal to a channel length of the primary channel.

2. The thin film transistor according to claim 1 , wherein, the at least one second sub-drain electrode comprises a plurality of second sub-drain electrodes.

3. The thin film transistor according to claim 1 , wherein, the channel length of the auxiliary channel is about 2 μm to 5 μm.

4. The thin film transistor according to claim 1 , wherein, a width of a side of each of the at least one second sub-drain electrode close to the primary channel is greater than or equal to a width of another side of that away from the primary channel.

5. The thin film transistor according to claim 4 , wherein, an included angle between the auxiliary channel and the primary channel is about 30° to 60°.

6. The thin film transistor according to claim 4 , wherein, an included angle between the auxiliary channel and the primary channel is about 90°.

7. The thin film transistor according to claim 1 , wherein, the primary channel is of a U-shaped structure comprising a bent portion and two extended portions connected to two ends of the bent portion respectively; the drain electrode comprises two strip-shaped arms corresponding to the two extended portions and a connecting arm corresponding to the bent portion; two ends of the connecting arm are configured to connect to the two strip-shaped arms, respectively; and, the auxiliary channel is formed in a portion of the drain electrode beyond the connecting arm.

8. The thin film transistor according to claim 7 , wherein, the auxiliary channel is formed at a junction of each of the two strip-shaped arms with the connecting arm.

9. An array substrate, comprising a substrate and a plurality of thin film transistors arranged on the substrate, wherein,
each of the plurality of thin film transistors comprises a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode;
the drain electrode comprises a first sub-drain electrode and at least one second sub-drain electrode are physically detached from one another, and a first portion of the active layer between the first sub-drain electrode and the source electrode, and a second portion of the active layer between each of the at least one second sub-drain electrode and the source electrode are used for forming different portions of a primary channel, respectively; and
the first sub-drain electrode is a signal input electrode, and a third portion of the active layer between the first sub-drain electrode and each of the at least one second sub-drain electrode is used for forming an auxiliary channel, a channel length of the auxiliary channel being less than or equal to a channel length of the primary channel.

10. A display device, comprising a backlight module and an array substrate arranged on the backlight module, wherein,
the array substrate comprises a substrate and a plurality of thin film transistors arranged on the substrate;
each of the plurality of thin film transistors comprises a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode;
the drain electrode comprises a first sub-drain electrode and at least one second sub-drain electrode that are physically detached from one another, and a first portion of the active layer between the first sub-drain electrode and the source electrode, and a second portion of the active layer between each of the at least one second sub-drain electrode and the source electrode are used for forming different portions of a primary channel, respectively; and
the first sub-drain electrode is a signal input electrode, and a third portion of the active layer between the first sub-drain electrode and each of the at least one second sub-drain electrode is used for forming an auxiliary channel, a channel length of the auxiliary channel being less than or equal to a channel length of the primary channel.

11. A method for manufacturing the thin film transistor according to claim 1 , comprising:
forming, on a substrate, a first conducting layer comprising the gate, the gate insulating layer, the active layer, and a second conducting layer comprising the source electrode and the drain electrode, wherein the drain electrode comprises the first sub-drain electrode and at least one second sub-drain electrode that are physically detached from one another, and the first portion of the active layer between the first sub-drain electrode and the source electrode and the second portion of the active layer between each of the at least one second sub-drain electrode and the source electrode are used for forming different portions of the primary channel, respectively; the first sub-drain electrode is a signal input electrode, and the third portion of the active layer between the first sub-drain electrode and each of the at least one second sub-drain electrode is used for forming the auxiliary channel, the channel length of the auxiliary channel being less than or equal to the channel length of the primary channel.

12. The thin film transistor according to claim 1 , wherein the at least one second sub-drain electrode includes one second sub-drain electrode, and the third portion of the active layer between the first sub-drain electrode and the second sub-drain electrode is used for forming the auxiliary channel.

13. The thin film transistor according to claim 2 , wherein the plurality of second sub-drain electrodes include two second sub-drain electrodes, the thin film transistor is a thin film transistor of an I-shaped structure, and the two second sub-drain electrodes are located on two opposite sides of the first sub-drain electrode respectively.

14. The thin film transistor according to claim 13 , wherein, a width of a side of each of the two second sub-drain electrode close to the primary channel is greater than or equal to a width of another side of that away from the primary channel.

15. The method for manufacturing the thin film transistor according to claim 11 , wherein, a half tone mask is used to form the primary channel and the auxiliary channel.

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Xiaoyuan
• Yang Ni
• Fang Yan
• Qi Zhijian
• Li Shaoru

Classifications

• H01L27/1255 Primary

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic

• H10D86/021

  of multiple TFTs · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title