Trench semiconductor device layout configurations

Patent metadata

Field	Value
Publication number	US-11245006-B2
Application number	US-201916724862-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Feb 23, 2015
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

First claim

The invention claimed is:

1. A trench semiconductor device comprising:
a layer of semiconductor material;
an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern comprising first and second parallel exterior trench portions that form first and third opposite sides of a first rectangle shape, and third and fourth parallel exterior trench portions connected to and perpendicular to the first and second parallel exterior trench portions that form second and fourth opposite sides of the first rectangle shape, each of the first, second, third and fourth exterior trench portions being lined with dielectric material and filled with conductive material;
a first interior trench pattern formed in the layer of semiconductor material, surrounded by the exterior trench pattern, the first interior trench pattern comprising first and second parallel interior trench portions that form first and third opposite sides of a second rectangle shape, and third and fourth parallel interior trench portions connected to and perpendicular to the first and second parallel interior trench portions that form second and fourth opposite sides of the second rectangle shape, each of the first, second, third and fourth interior trench portions being lined with dielectric material and filled with conductive material;
a second interior trench pattern formed in the layer of semiconductor material, surrounded by the exterior trench pattern, wherein the second interior trench pattern comprising fifth and sixth parallel interior trench portions that form first and third opposite sides of a third rectangle shape, and seventh and eighth parallel interior trench portions connected to and perpendicular to the fifth and sixth parallel interior trench portions that form second and fourth opposite sides of the third rectangle shape, each of the fifth, sixth, seventh and eighth interior trench portions being lined with dielectric material and filled with conductive material; and
a third interior trench pattern formed in the layer of semiconductor material, surrounded by the exterior trench pattern, wherein the third interior trench pattern comprising ninth and tenth parallel interior trench portions that form first and third opposite sides of a fourth rectangle shape, and eleventh and twelfth parallel interior trench portions connected to and perpendicular to the ninth and tenth parallel interior trench portions that form second and fourth opposite sides of the fourth rectangle shape, each of the ninth, tenth, eleventh and twelfth interior trench portions being lined with dielectric material and filled with conductive material,
wherein the first interior trench pattern, the second interior trench pattern and the third interior trench pattern are parallel to each other, and
wherein the second interior trench pattern is between the first interior trench pattern and the third interior trench pattern.

2. The trench semiconductor device of claim 1 , wherein the first exterior trench portion is parallel to the first interior trench portion.

3. The trench semiconductor device of claim 1 , wherein the first exterior trench portion is parallel to the fifth interior trench portion.

4. The trench semiconductor device of claim 1 , wherein the first and second interior trench patterns are separated from each other by an interior gap distance of about 2.0 μm.

5. The trench semiconductor device of claim 1 , wherein the fifth, the sixth, the seventh and the eighth interior trench portions each have a trench width of about 1.4 μm.

6. The trench semiconductor device of claim 5 , wherein the first, the second, the third and the fourth interior trench portions each have a trench width of about 1.4 μm.

7. The trench semiconductor device of claim 1 , wherein the first interior trench portion and the fifth interior trench portion are spaced from the first exterior trench portion by a gap distance of about 2.0 μm.

8. The trench semiconductor device of claim 1 , wherein the first exterior trench portion is parallel to the ninth interior trench portion.

9. The trench semiconductor device of claim 1 , wherein the first, second and third interior trench patterns are separated from each other by an interior gap distance of about 2.0 μm.

10. The trench semiconductor device of claim 1 , wherein the ninth, the tenth, the eleventh and the twelfth interior trench portions each have a trench width of about 1.4 μm.

11. The trench semiconductor device of claim 10 , wherein the fifth, the sixth, the seventh and the eighth interior trench portions each have a trench width of about 1.4 μm.

12. The trench semiconductor device of claim 11 , wherein the first, the second, the third and the fourth interior trench portions each have a trench width of about 1.4 μm.

13. The trench semiconductor device of claim 1 , wherein the first, the second, the third and the fourth interior trench portions each have a trench width of about 1.4 μm.

14. The trench semiconductor device of claim 1 , wherein the first interior trench portion is spaced from the first exterior trench portion by a gap distance of about 2.0 μm.

15. The trench semiconductor device of claim 1 , wherein the first and second parallel exterior trench portions that form the first and third opposite sides of the first rectangle shape form long sides of the first rectangle shape, and
wherein the third and fourth parallel exterior trench portions that form the second and fourth opposite sides of the first rectangle shape form short sides of the first rectangle shape.

16. The trench semiconductor device of claim 15 , wherein the first and second parallel interior trench portions that form the first and third opposite sides of the second rectangle shape form short sides of the second rectangle shape, and
wherein the third and fourth parallel interior trench portions that form the second and fourth opposite sides of the second rectangle shape form short sides of the second rectangle shape.

17. The trench semiconductor device of claim 1 , wherein the first, fifth and ninth interior trench portions are each separated from the first exterior trench portion by an equal distance.

18. The trench semiconductor device of claim 17 , wherein the second, sixth and tenth interior trench portions are each separated from the second exterior trench portion by an equal distance.

19. The trench semiconductor device of claim 1 , wherein the first exterior trench portion is parallel to the first interior trench portion,
wherein the first exterior trench portion is parallel to the fifth interior trench portion, and
wherein the first exterior trench portion is parallel to the ninth interior trench portion.

20. The trench semiconductor device of claim 1 , wherein the first interior trench portion, the fifth interior trench portion, and the ninth interior trench portion are each separated from the first exterior trench portion by a first distance,
wherein the second interior trench portion, the sixth interior trench portion, and the tenth interior trench portion are each separated from the second exterior trench portion by a second distance, and
wherein the first distance and the second distance are equal.

Assignees

• Polar Semiconductor Llc
• Sanken Electric Co Ltd

Inventors

• Dosev Dosi
• Rankila Don
• Kamimura Tatsuya
• Fukunaga Shunsuke
• Kosier Steven L
• West Peter

Classifications

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/665

  having edge termination structures · CPC title

• H10D62/126 Primary

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H01L29/0653

  Electricity · mapped topic