Chip including a scribe lane

Patent metadata

Field	Value
Publication number	US-11244911-B2
Application number	US-201916389367-A
Country	US
Kind code	B2
Filing date	Apr 19, 2019
Priority date	Oct 18, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a substrate comprising:
a main chip region; and
a scribe lane surrounding the main chip region;

a lower interlayer insulating layer disposed on the substrate in the scribe lane;
a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and
a pad structure disposed on the lower interlayer insulating layer and comprising a low-k dielectric pattern, an upper interlayer insulating pattern, and a metal pad layer,
wherein the circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.

2. The semiconductor chip of claim 1 , wherein a distance between the circuit structure and the pad structure in the longitudinal direction of the scribe lane is 8 μm or less.

3. The semiconductor chip of claim 1 , wherein the pad structure comprises a first pad structure disposed on a first side of the circuit structure and a second pad structure disposed on a second side opposite to the first side along the longitudinal direction.

4. The semiconductor chip of claim 3 , wherein a first distance between the circuit structure and the first pad structure is equal to a second distance between the circuit structure and the second pad structure.

5. The semiconductor chip of claim 3 , wherein a first distance between the circuit structure and the first pad structure is different from a second distance between the circuit structure and the second pad structure.

6. The semiconductor chip of claim 3 , wherein one of the first pad structure or the second pad structure is in contact with the circuit structure and the other one of the first pad structure or the second pad structure is disposed to be spaced apart from the circuit structure.

7. The semiconductor chip of claim 1 ,
wherein a distance between the metal pad layer and the circuit structure in the longitudinal direction of the scribe lane is 8 μm or less.

8. The semiconductor chip of claim 1 , wherein the circuit structure comprises:
a low-k dielectric layer;
an upper interlayer insulating layer; and
a passivation layer, the low-k dielectric layer, the upper interlayer
insulating layer and the passivation layer being sequentially stacked,
wherein the metal pad layer comprises:
a first metal pad layer disposed on a first side of the passivation layer along the longitudinal direction; and
a second metal pad layer disposed on a second side opposite to the first side of the passivation layer along the longitudinal direction,
wherein the first metal pad layer disposed on the first side of the passivation layer is in contact with the passivation layer, and
wherein the second metal pad layer disposed on the second side of the passivation layer is disposed to be spaced apart from the passivation layer.

9. The semiconductor chip of claim 1 ,
wherein the circuit structure comprises:
a low-k dielectric layer;
an upper interlayer insulating layer; and
a passivation layer, the low-k dielectric layer, the upper interlayer insulating layer and the passivation layer being sequentially stacked, and

wherein the semiconductor further comprises a via disposed on the passivation layer.

10. The semiconductor chip of claim 9 , wherein a distance between the via and the circuit structure in the longitudinal direction of the scribe lane is 8 μm or less.

11. The semiconductor chip of claim 1 , wherein the circuit structure comprises:
a low-k dielectric layer;
an upper interlayer insulating layer; and
a passivation layer, the low-k dielectric layer, the upper interlayer insulating layer and the passivation layer being sequentially stacked, and
wherein the passivation layer comprises:
a first insulating layer;
a second insulating layer; and
a third insulating layer, the first insulating layer, the second insulating layer and the third insulating layer being sequentially stacked, and
wherein the first insulating layer and the third insulating layer comprise oxide and the second insulating layer comprises nitride.

12. The semiconductor chip of claim 1 , wherein an open region is provided directly between the circuit structure and the pad structure in the longitudinal direction, such that a side face of the circuit structure directly opposes a side face of the pad structure in the longitudinal direction.

13. A semiconductor chip comprising:
a substrate comprising:
a main chip region; and
a scribe lane surrounding the main chip region;

a stacked structure extending along a longitudinal direction of the scribe lane, provided on the substrate in the scribe lane and comprising a low-k dielectric material;
an open region in which the stacked structure is partially removed; and
a pad structure disposed in the open region and comprising a low-k dielectric pattern, an upper interlayer insulating pattern, and a metal pad layer,
wherein the pad structure is disposed to be spaced apart from the stacked structure in the longitudinal direction of the scribe lane.

14. The semiconductor chip of claim 13 , wherein a distance between the stacked structure and the pad structure in the longitudinal direction of the scribe lane is 8 μm or less.

15. The semiconductor chip of claim 13 ,
wherein a distance between the metal pad layer and the stacked structure in the longitudinal direction of the scribe lane is 8 μm or less.

16. The semiconductor chip of claim 13 , wherein the pad structure is disposed on each side of the stacked structure along the longitudinal direction and comprises:
a first pad structure; and
a second pad structure,
wherein the first pad structure disposed on a first side of the stacked structure is in contact with the stacked structure, and
wherein the second pad structure disposed on a second side opposite to the first side is disposed to be spaced apart from the stacked structure.

17. The semiconductor chip of claim 13 , wherein the open region is provided directly between the stacked structure and the pad structure in the longitudinal direction, such that a side face of the stacked structure directly opposes a side face of the pad structure in the longitudinal direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yoon Sung
• Kim Yun Hee
• Bae byung moon
• Sim Hyun Su
• Yoon Jun Ho
• Choi Jung Ho

Classifications

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/603

  Formed on wafers or substrates before dicing and remaining on chips after dicing · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title