Method of manufacturing semiconductor device and semiconductor device

Patent metadata

Field	Value
Publication number	US-9837326-B2
Application number	US-201615245700-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Aug 27, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing a semiconductor substrate that includes a first pad electrode and a second pad electrode, the first pad electrode being formed at an uppermost layer of a plurality of wiring layers and having a first metal film formed on a surface of the first pad electrode, and the second pad electrode being electrically connected to the first pad electrode, being formed at the uppermost layer of the plurality of wiring layers and having a second metal film formed on a surface of the second pad electrode;
(b) forming a first insulating film having a first opening for exposing the first metal film in the first pad electrode, and a second opening for exposing the second metal film in the second pad electrode;
(c) forming a mask layer on the first insulating film for covering the first opening and exposing the second opening;
(d) forming a wiring which is electrically connected to the second pad electrode via the second opening;
(e) forming a second insulating film on the first pad electrode and on the wiring;
(f) forming a third opening in the second insulating film above the first pad electrode and forming a fourth opening of the second insulating film above the wiring while leaving an organic reaction layer on each surface of the first pad electrode and the wiring;
(g) performing heat processing on the semiconductor substrate after the step (f), while maintaining the organic reaction layer on each surface of the first pad electrode and the wiring; and
(h) forming a bump on the wiring in the fourth opening.

2. The method of manufacturing the semiconductor device according to claim 1 ,
wherein the first opening is exposed by removing the mask layer, and further, a conductive layer on the first metal film is removed by etching while leaving the first metal film of the first pad electrode after the step (d).

3. The method of manufacturing the semiconductor device according to claim 2 ,
wherein the conductive layer is formed of a different material from the first metal film.

4. The method of manufacturing the semiconductor device according to claim 1 ,
wherein a temperature of the heat processing in the step (g) is higher than a melting point of the bump.

5. The method of manufacturing the semiconductor device according to claim 1 ,
further comprising performing a first probe test by bringing a probe needle in contact with the first pad electrode between the step (f) and the step (g).

6. The method of manufacturing the semiconductor device according to claim 1 ,
further comprising performing a second probe test by bringing a probe needle in contact with the first pad electrode after the step (g), while maintaining the organic reaction layer on each surface of the first pad electrode and the wiring.

7. The method of manufacturing the semiconductor device according to claim 1 ,
further comprising removing the organic reaction layer from the surface of the wiring after the step (g) before the step (h).

8. The method of manufacturing the semiconductor device according to claim 1 ,
wherein the heat processing in the step (g) is a baking test of a non-volatile memory which is formed in a region of a semiconductor chip of the semiconductor substrate.

9. The method of manufacturing the semiconductor device according to claim 1 ,
wherein a size of the first opening viewed in a plan view is larger than a size of the second opening viewed in a plan view.

10. The method of manufacturing the semiconductor device according to claim 1 , further comprising:
after step (h), dicing the semiconductor substrate to form the semiconductor device including the first pad electrode, the second pad electrode, and the bump on the wiring to electrically connect to the first and second pad electrodes.

11. A semiconductor device comprising:
a semiconductor chip having a main surface in which a semiconductor circuit is formed;
a plurality of first pad electrodes electrically connected to the semiconductor circuit and covered by a plurality of metal films, respectively;
a plurality of second pad electrodes electrically connected to the plurality of first pad electrodes, respectively, and formed on the same layer with each of the plurality of first pad electrodes;
a plurality of wirings covering each of the plurality of second pad electrodes and electrically connected to the plurality of second pad electrodes, respectively;
an insulating film formed on the plurality of wirings; and
a plurality of bumps provided in opening portions of the respective insulating films of the plurality of wirings,
wherein each surface of the plurality of metal films is exposed and each metal film has a hole piercing therethrough.

12. The semiconductor device according to claim 11 ,
wherein
each metal film extends on one of the plurality of second pad electrodes.

13. The semiconductor device according to claim 11 ,
wherein each of the plurality of first pad electrodes is arranged on an end portion side of the semiconductor chip,
each of the plurality of second pad electrodes is arranged at an inner side than each of the plurality of first pad electrodes, and
the wiring is led out from each of the plurality of second pad electrodes arranged at the inner side.

14. The semiconductor device according to claim 11 ,
wherein the semiconductor circuit includes a non-volatile memory circuit.

15. The semiconductor device according to claim 11 ,
further comprising a plurality of metal wires including ends connected to the plurality of first pad electrodes, respectively, portions of plurality of metal wires spaced-apart from the semiconductor chip.

Assignees

• Renesas Electronics Corp

Inventors

• Yajima Akira

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title