Semiconductor device having crack-resisting ring structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9559063-B2
Application number	US-201313946015-A
Country	US
Kind code	B2
Filing date	Jul 19, 2013
Priority date	Jul 25, 2012
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A semiconductor device includes an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
an interlayer insulating layer disposed over the semiconductor substrate and including a plurality of wiring layers;
a scribe line region located over a portion of the interlayer insulating layer,
a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate;
a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and
a protective film disposed over the interlayer insulating layer and covering the crack lead ring and the seal ring, but not covering the scribe line region,
wherein the crack lead ring includes an uppermost layer wiring in an uppermost wiring layer of said plurality of wiring layers,
wherein when the crack lead ring has a wiring in an underlayer below the uppermost wiring layer, the uppermost layer wiring extends in a direction away from the circuit region towards an outside of the semiconductor device, relative to the wiring in the underlayer, and
wherein the protective film has an end overlapped with an end of the uppermost layer wiring nearest the scribe line region, the end of the protective film not overlapping the scribe line region, and wherein the protective film forms a step over the interlayer insulating layer, at an edge of the scribe line region.

2. The semiconductor device according to claim 1 ,
wherein the crack lead ring further comprises:
a guard ring as said wiring of the underlayer, continuously formed over one or more wiring layers connected by via holes, from the uppermost wiring layer toward the semiconductor substrate.

3. The semiconductor device according to claim 2 ,
wherein the uppermost layer wiring extends farther toward the outside, as compared with the guard ring.

4. The semiconductor device according to claim 3 ,
wherein a width of the uppermost layer wiring is twice as broad as a width of the guard ring.

5. The semiconductor device according to claim 2 ,
wherein the guard ring reaches the semiconductor substrate from the uppermost wiring layer.

6. The semiconductor device according to claim 2 ,
wherein a plurality of guard rings are disposed from the seal ring side toward the outside.

7. The semiconductor device according to claim 1 ,
wherein the uppermost layer wiring includes:
a lower wiring; and
an upper wiring disposed over the lower wiring, and
wherein an end of the upper wiring includes a protrusion protruded upward from an uppermost surface of the interlayer insulating layer.

8. The semiconductor device according to claim 1 ,
wherein the protective film includes:
a passivation film disposed to cover the crack lead ring and the seal ring; and
a heat resistant film disposed to cover the passivation film,
wherein ends of the passivation film and the heat resistant film overlap with an end of the uppermost layer wiring.

9. The semiconductor device according to claim 1 ,
wherein a plurality of seal rings are disposed outward from the circuit region side, and
wherein a distance between a first seal ring adjacent to the crack lead ring and the crack lead ring, is larger than a distance from the first seal ring to an adjacent second seal ring.

10. The semiconductor device according to claim 1 ,
wherein the crack lead ring further includes:
a guard ring as said wiring of the underlayer, continuously formed over one or more wiring layers from the uppermost wiring layer toward the semiconductor substrate through a via hole,
wherein the uppermost layer wiring includes:
a lower wiring; and
an upper wiring disposed over the lower wiring,
wherein an end of the upper wiring includes a protrusion protruded upward from an uppermost surface of the interlayer insulating layer,

wherein the protective film includes:
a passivation film disposed to cover the crack lead ring and the seal ring; and
a heat resistant film disposed to cover the passivation film, and

wherein ends of the passivation film and the heat resistant film overlap with the protrusion.

11. A method for manufacturing a semiconductor device, comprising the steps of:
forming, over a semiconductor substrate, an interlayer insulating layer including a plurality of wiring layers, a seal ring surrounding a circuit region over the semiconductor substrate, and a crack lead ring having an uppermost layer wiring in an uppermost wiring layer of the plurality of wiring layers; and
forming, over the interlayer insulating layer, a protective film covering the uppermost layer wiring and the seal ring,
wherein when the crack lead ring has a wiring in an underlayer below the uppermost wiring layer, the uppermost layer wiring extends in a direction away from the circuit region towards a scribe line region at an outside of the semiconductor device, relative to the wiring in the underlayer, and
wherein the step of forming the protective film includes:
a step of forming the protective film so that:
an end of the protective film overlaps an end of the uppermost layer wiring nearest the scribe line region, the end of the protective film not overlapping the scribe line region, and wherein the protective film forms a step over the interlayer insulating layer, at an edge of the scribe line region.

12. A semiconductor device, comprising:
a semiconductor substrate;
an interlayer insulating layer disposed over the semiconductor substrate and including a plurality of wiring layers, the plurality of wiring layers including an uppermost wiring layer;
a scribe line region located over a portion of the interlayer insulating layer;
a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate;
a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring, the crack lead ring including an uppermost layer wiring formed in the uppermost wiring layer, the uppermost layer wiring extending in a direction away from the circuit region towards the scribe line region and terminating in an end; and
a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring, the protective film overlapping the end of the uppermost layer wiring but not overlapping the scribe line region and thereby forming a step at an edge of the scribe line region.

13. The semiconductor device according to claim 12 , wherein the crack lead ring further comprises:
a guard ring surrounding the seal ring, the guard ring being connected to the uppermost layer wiring and disposed closer to the seal ring than to an intermediate position, in a width direction, of the uppermost layer wiring.

14. The semiconductor device according to claim 13 , wherein:
the guard ring comprises alternating wiring layers and via holes, and extends from the uppermost layer wiring toward the semiconductor substrate.

15. The semiconductor device according to claim 13 , wherein the guard ring reaches the semiconductor substrate from the uppermost layer wiring.

16. The semiconductor device according to claim 13 , wherein the guard ring does not reach the semiconductor substrate from the uppermost layer wiring.

17. The semiconductor device according to claim 13 , comprising a plurality of concentric guard rings surrounding the seal ring, each guard ring connected to the uppermost layer wiring.

18. The semiconductor device according to claim 17 , wherein:
at least one of said plurality of guard rings reaches semiconductor substrate from the uppermost layer wiring; an

Assignees

• Renesas Electronics Corp

Inventors

• Watanabe Takeshi
• Ishii Junya
• Saitou Hirofumi
• Kitajima Hiroyasu
• Kojima Tatsuki
• Kawashima Yoshitsugu

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H01L2924/0002

  Electricity · mapped topic