Mitigating disturbances of memory cells

Patent metadata

Field	Value
Publication number	US-11244733-B2
Application number	US-201916685309-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Aug 4, 2017
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

First claim

What is claimed is:

1. A method, comprising:
forming an array of memory cells, each memory cell comprising a bottom electrode, a ferroelectric material, and a top electrode;
forming a plate coupled to the array of memory cells;
etching through the plate and at least a portion of a selected memory cell to expose the bottom electrode of the selected memory cell; and
forming a contact to couple the bottom electrode of the memory cell and the plate.

2. The method of claim 1 , wherein forming the contact further comprises:
depositing a first material having a first resistance;
etching a portion of the first material; and
depositing a second material having a second resistance lower than the first resistance in an area etched free of the first material.

3. The method of claim 1 , further comprising:
depositing a dielectric layer on top of the contact.

4. The method of claim 3 , further comprising:
forming a metal layer directly above the contact, wherein the dielectric layer is positioned between a top surface of the contact and the metal layer.

5. The method of claim 3 , further comprising:
forming a metal layer that does not extend above the contact.

6. The method of claim 1 , wherein forming each memory cell of the array of memory cells comprises:
depositing a first dielectric material on a substrate;
etching a container into the first dielectric material; and
depositing a first material into the container to form the bottom electrode.

7. The method of claim 6 , wherein forming the memory cell further comprises:
etching at least a portion of the first material in the container.

8. The method of claim 7 , wherein forming the memory cell further comprises:
depositing the ferroelectric material into the container onto the bottom electrode after etching the at least the portion of the first material in the container.

9. The method of claim 8 , wherein forming the memory cell further comprises:
depositing the first material the container onto the ferroelectric material to form at least a portion of the top electrode.

10. The method of claim 9 , wherein forming the memory cell further comprises:
etching at least a portion of the ferroelectric material in the container before depositing the first material into the container.

11. The method of claim 9 , wherein forming the memory cell further comprises:
depositing a second material into the container onto the first material of the top electrode to form a second portion of the top electrode.

12. The method of claim 11 , wherein forming the memory cell further comprises:
etching at least a portion of the first material in the container before depositing the second material into the container.

13. The method of claim 6 , wherein forming the memory cell further comprises:
etching or planarizing the memory cell to form a top planar surface of the memory cell.

14. The method of claim 13 , wherein forming the plate comprises:
depositing the first material on the top planar surface to form a first layer of the plate;
etching at least a portion of the first material on the top planar surface; and
depositing a second material into an area of the first material that was etched away to form a second layer of the plate.

15. The method of claim 7 , wherein forming the memory cell further comprises:
depositing a dielectric material into the container onto the bottom electrode after etching the at least the portion of the first material in the container.

16. A method, comprising:
forming an array of memory cells at least partially surrounded by a first dielectric material;
forming a second dielectric material above the first dielectric material;
forming a plate coupled to each memory cell of the array of memory cells; and
forming a contact to couple a bottom electrode of at least one memory cell of the array of memory cells with the plate, wherein forming the contact further comprises:
depositing a first material comprising titanium nitride;
etching a portion of the first material; and
depositing a second material comprising tungsten in an area etched free of the first material.

17. The method of claim 16 , further comprising:
forming an intermediate material between the first dielectric material and the second dielectric material.

18. The method of claim 16 , wherein the bottom electrode is coupled with a digit line associated with the array of memory cells.

19. A method, comprising:
forming an array of memory cells, each memory cell comprising a bottom electrode, a ferroelectric material, and a top electrode;
forming a contact at an edge of the array of memory cells to couple a first bottom electrode of a first memory cell of the array of memory cells with a plate, wherein the contact has a first height above a surface of the plate; and
forming a metal layer at about the same height above the surface of the plate.

Assignees

• Micron Technology Inc

Inventors

• Vimercati Daniele
• Fischer Mark
• Johnson Adam D

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title