Dynamic memory rank configuration

Patent metadata

Field	Value
Publication number	US-11244727-B2
Application number	US-201514940084-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Nov 29, 2006
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

First claim

What is claimed is:

1. A method of controlling a memory module having memory components disposed thereon, the method comprising:
outputting first and second memory read commands to the memory module at respective times;
receiving first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command; and
receiving second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa, and the first plurality of the memory components including at least one other memory component that is also included in the second plurality of the memory components.

2. The method of claim 1 further comprising outputting a maintenance command to the at least one memory component included in the first plurality of the memory components but not included in the second plurality of the memory components, the maintenance command instructing the at least one memory component to execute a maintenance operation during an interval that transpires concurrently with receiving the second read data from the second plurality of the memory components.

3. The method of claim 1 wherein outputting the first and second memory read commands to the memory module at respective times comprises outputting the first and second memory read commands to a dual inline memory module (DIMM) at respective times via a command/address path coupled in common to all the memory components included in the first and second pluralities.

4. The method of claim 1 wherein outputting the first and second memory read commands to the memory module at respective times comprises outputting the first and second memory read commands to first and second pluralities of nonvolatile memory components.

5. The method of claim 4 wherein the nonvolatile memory components comprise Flash memory components.

6. The method of claim 1 wherein outputting the first and second memory read commands to the memory module at respective times comprises, at a first time, outputting chip-select signals exclusively to the first plurality the components while outputting first command signals on a command signaling path coupled to each of the memory components of the first and second pluralities, and, at a second time, outputting chip-select signals exclusively to the second plurality of the memory components while outputting second command signals on the command signaling path.

7. The method of claim 1 further comprising outputting a third memory read command to the memory module after outputting the first and second memory read commands, and receiving third read data from the third plurality of memory components via a third plurality of data paths, respectively, in response to the third memory read command, the third plurality of memory components including (i) at least one memory component not included in the first plurality of memory components and (ii) at least one other memory component not included in the second plurality of memory components.

8. The method of claim 1 wherein the at least one memory component included in the first plurality of the memory components but not included in the second plurality of the memory components comprises a first memory component of a virtual pair of components, and the at least one memory component included in the second plurality of the memory components but not included in the first plurality of the memory components comprises a second memory component of the virtual pair of components, the method further comprising copying data from the first memory component of the virtual pair to the second memory component of the virtual pair.

9. The method of claim 1 wherein outputting the first memory command to the memory module comprises receiving a request to read data from the memory module, obtaining a value that indicates the first plurality of memory components and outputting chip-select signals exclusively to the first plurality of the memory components.

10. The method of claim 9 wherein obtaining the value that indicates the first plurality of memory components comprises obtaining the value from a page table based at least in part on an address received in association with the request to read data.

11. A memory control component comprising:
control logic to output first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon; and
interface circuitry to receive (i) first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and (ii) second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa, and the first plurality of the memory components including at least one other memory component that is also included in the second plurality of the memory components.

12. The memory control component of claim 11 wherein the control logic to output first and second memory read commands to the memory module is further to output a maintenance command to the at least one memory component included in the first plurality of the memory components but not included in the second plurality of the memory components, the maintenance command instructing the at least one memory component to execute a maintenance operation during an interval that transpires concurrently with receiving the second read data from the second plurality of the memory components.

13. The memory control component of claim 11 wherein the control logic to output first and second memory read commands to a memory module outputs the first and second memory read commands to a dual inline memory module (DIMM) at respective times via a command/address path coupled in common to all the memory components included in the first and second pluralities.

14. The memory control component of claim 11 wherein the control logic to output the first and second memory read commands to the memory module at respective times comprises circuitry to output the first and second memory read commands to first and second pluralities of nonvolatile memory components.

15. The memory control component of claim 14 wherein the nonvolatile memory components comprise Flash memory components.

16. The memory control component of claim 11 wherein the control logic to output the first and second memory read commands to the memory module at respective times comprises circuitry to output, at a first time, chip-select signals exclusively to the first plurality the components while outputting first command signals on a command signaling path coupled to each of the memory components of the first and second pluralities, and to output, at a second time, chip-select signals exclusively to the second plurality of the memory components while outputting second command signals on the command signaling path.

17. The memory control component of claim 11 wherein the control logic to output the first and second memory read commands is additionally to output a third memory read command to the memory module after outp

Assignees

• Rambus Inc

Inventors

• Bronner Gary B
• Haukness Brent S
• Horowitz Mark A
• Kellam Mark D
• Assaderaghi Fariborz

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C13/0035

  Evaluating degradation, retention or wearout, e.g. by counting writing cycles · CPC title