Non-linearity correction

Patent metadata

Field	Value
Publication number	US-11239854-B2
Application number	US-202017061730-A
Country	US
Kind code	B2
Filing date	Oct 2, 2020
Priority date	Oct 3, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

First claim

What is claimed is:

1. A non-linearity correction circuit, comprising:
a non-linearity coefficient estimation circuit comprising:
a data capture circuit;
a non-linearity term generation circuit coupled to the data capture circuit;
a time-to-frequency conversion circuit coupled to the data capture circuit and the non-linearity term generation circuit;
a bin identification circuit coupled to the time-to-frequency conversion circuit;
a residual non-linearity conversion circuit coupled to the bin identification circuit; and
a non-linearity coefficient generation circuit coupled to the bin identification circuit and the residual non-linearity conversion circuit.

2. The non-linearity correction circuit of claim 1 , further comprising a non-linearity corrector circuit coupled to the non-linearity coefficient estimation circuit, and configured to generate non-linearity corrected data based on non-linearity correction coefficients generated by the non-linearity coefficient generation circuit.

3. The non-linearity correction circuit of claim 2 , wherein the data capture circuit is configured to capture the non-linearity corrected data.

4. The non-linearity correction circuit of claim 2 , wherein the data capture circuit is configured to capture raw data samples provided as input to the non-linearity corrector circuit for non-linearity correction.

5. The non-linearity correction circuit of claim 1 , wherein the non-linearity term generation circuit is configured to generate non-linearity terms for the data captured by the data capture circuit.

6. The non-linearity correction circuit of claim 5 , wherein the time-to-frequency conversion circuit is configured to convert the non-linearity terms and data captured by the data capture circuit from time domain to frequency domain.

7. The non-linearity correction circuit of claim 5 , wherein:
the non-linearity coefficient generation circuit is configured to estimate non-linearity coefficients based on frequency responses of the non-linearity terms and frequency response of output of the data capture circuit at frequency bins identified by the bin identification circuit; and
at each bin identified by the bin identification circuit, the frequency responses of the non-linearity terms serve as weights of the non-linearity coefficients; and the frequency response of the output of the data capture circuit serves as a measurement in the estimate of the non-linearity coefficients.

8. The non-linearity correction circuit of claim 5 , wherein the bin identification circuit is configured to identify frequency bins to apply in estimation of non-linearity correction coefficients as bins having signal power below a first threshold and non-linearity term power above a second threshold.

9. The non-linearity correction circuit of claim 8 , wherein the residual non-linearity conversion circuit is configured to modify frequency response of a signal at the frequency bins by adding a plurality of correction terms to the signal wherein each correction term is a product of frequency response of the non-linearity terms with corresponding non-linearity correction coefficients.

10. The non-linearity correction circuit of claim 1 , wherein:
the data capture circuit is a first data capture circuit;
the time-to-frequency conversion circuit is a first time-to-frequency conversion circuit; and
the non-linearity correction circuit further comprises:
a data path comprising:
a first digital step attenuator (DSA); and
a first analog-to-digital converter (ADC) coupled to the first data capture circuit; and

a reference path comprising:
a second DSA comprising an input coupled to an input of the first DSA;
a second ADC coupled to the second DSA;
a second data capture circuit coupled to the second ADC;
a second time-to-frequency conversion circuit coupled to the second data capture circuit;
a channel estimation circuit coupled to the first time-to-frequency conversion circuit and the second time-to-frequency conversion circuit;
a channel equalization circuit coupled to the channel estimation circuit and the second time-to-frequency conversion circuit; and
a source non-linearity subtraction circuit coupled to the channel equalization circuit, the first time-to-frequency conversion circuit, and the bin identification circuit.

11. The non-linearity correction circuit of claim 10 , wherein the channel equalization circuit is configured to equalize the reference path to the data path.

12. The non-linearity correction circuit of claim 10 , wherein the channel estimation circuit comprises:
a base channel memory;
a slope memory;
an intercept memory;
a raw channel estimation circuit configured to generate a raw channel estimate based on output of the first ADC and output of the second ADC;
a base channel removal circuit coupled to the raw channel estimation circuit and the base channel memory;
a slope and intercept estimation circuit coupled to the base channel removal circuit, the slope memory, and the intercept memory; and
a base channel estimator coupled to the slope and intercept estimation circuit and the base channel memory.

13. The non-linearity correction circuit of claim 12 wherein the channel equalization circuit comprises a computation circuit configured to:
compute a channel equalization value as a product of:
a base channel value retrieved from the base channel memory; and
a sum of an intercept value retrieved from the intercept memory and a slope value retrieved from the slope memory multiplied by a frequency bin index; and

compute an equalized data value as a product of the channel equalization value and a frequency domain data value produced by the second time-to-frequency conversion circuit.

14. A non-linearity correction circuit, comprising:
a data path comprising:
a first digital step attenuator (DSA);
a first analog-to-digital converter (ADC);
a first data capture circuit coupled to the first ADC; and
a first time-to-frequency conversion circuit coupled to the first data capture circuit;

a reference path comprising:
a second DSA comprising an input coupled to an input of the first DSA;
a second ADC coupled to the second DSA;
a second data capture circuit coupled to the second ADC;
a second time-to-frequency conversion circuit coupled the second data capture circuit;
a channel estimation circuit coupled to the first time-to-frequency conversion circuit and the second time-to-frequency conversion circuit;
a channel equalization circuit coupled to the channel estimation circuit and the second time-to-frequency conversion circuit; and
a source non-linearity subtraction circuit coupled to the channel equalization circuit and the first time-to-frequency conversion circuit; and

a non-linearity term generation circuit coupled to the first data capture circuit and the first time-to-frequency conversion circuit;
a bin identification circuit coupled to the source non-linearity subtraction circuit and the first time-to-frequency conversion circuit;
a residual non-linearity conversion circuit coupled to the bin identification circuit; and
a non-linearity coefficient generation circuit coupled to the bin identification circuit and the residual non-linearity conversion circuit.

15. The non-linearity correction circuit of claim 14 , wherein:
the non-linearity coefficient generation circuit is configured to estimate non-linearity coefficients based on frequency responses of non-linearity terms generated by the non-linearity term generation circuit and output of the source non-linearity subtraction circuit at frequency bins identified by the bin

Assignees

• Texas Instruments Inc

Inventors

• Tangudu Jawaharlal
• Gupta Pankaj
• Potty Sreenath Narayanan
• Paulose Ajai
• Sriram Chandrasekhar
• Varma Mahesh Ravi
• Vejlani Shabbar Abbasi
• Shrivastava Neeraj
• Varshney Himanshu
• Patel Divyeshkumar Mahendrabhai
• Chaudhari Raju Kharataram

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/1038

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/367 Primary

  Non-linear conversion · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03M1/1235

  Non-linear conversion not otherwise provided for in subgroups of H03M1/12 · CPC title