Method and system for packing optimization of semiconductor devices

Patent metadata

Field	Value
Publication number	US-11239192-B2
Application number	US-202016943015-A
Country	US
Kind code	B2
Filing date	Jul 30, 2020
Priority date	Aug 10, 2016
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

First claim

What is claimed:

1. An apparatus, comprising:
a substrate having a first surface and a second surface opposite the first surface, wherein the second surface comprises isosceles wedge-shaped regions bounded by first radial reference lines that radiate from a radial origin of the second surface and define an acute central angle of each isosceles wedge-shaped region at the radial origin; and
first interconnects arranged in each of the isosceles wedge-shaped regions, wherein each first interconnect includes a minor axis and a major axis greater than its respective minor axis, and wherein the major axis of each first interconnect in its respective isosceles wedge-shaped region is parallel to a second radial reference line that radiates from the radial origin and bisects the respective isosceles wedge-shaped region.

2. The apparatus of claim 1 , further comprising:
second interconnects, each second interconnect comprising a minor axis and a major axis greater than its respective minor axis;
wherein the second surface of the substrate comprises a first perimeter edge; and
wherein each second interconnect is arranged along the first perimeter edge of the second surface such that the major axis of each second interconnect is parallel to the first perimeter edge of the second surface.

3. The apparatus of claim 1 , further comprising:
second interconnects, each second interconnect comprising a minor axis and a major axis greater than its respective minor axis;
wherein the second surface of the substrate comprises a perimeter edge with one or more corners; and
wherein each second interconnect is arranged along a first corner of the one or more corners such that the major axis of each second interconnect is perpendicular to a third radial reference line that radiates from the radial origin and through the first corner of the one or more corners.

4. The apparatus of claim 1 , wherein:
the substrate comprises a semiconductor die; and
the first interconnects are electrically connected to circuitry of the semiconductor die.

5. The apparatus of claim 1 , further comprising:
a semiconductor die connected to the first surface of the substrate; and
wherein the first interconnects are electrically connected to circuitry of the semiconductor die via the substrate.

6. The apparatus of claim 1 , wherein each first interconnect is elliptical.

7. The apparatus of claim 1 , wherein each isosceles wedge-shaped region is an isosceles triangular-shaped region.

8. The apparatus of claim 1 , wherein every interconnect in a respective isosceles wedge-shaped region comprises a major axis that is parallel to its respective second radial reference line.

9. The apparatus of claim 1 , wherein:
each of the first interconnects of a respective isosceles wedge-shaped region lie on the second radial reference line of the respective isosceles wedge-shaped region; and
each isosceles wedge-shaped region further includes second interconnects not lying on its second radial reference line; and
a major axis of each second interconnect in its respective isosceles wedge-shaped region is parallel to the second radial reference line of the respective isosceles wedge-shaped region.

10. The apparatus of claim 1 , wherein the acute central angles of the isosceles wedge-shaped regions sum to 360°.

11. An apparatus, comprising:
a substrate having a first surface and a second surface opposite the first surface; and
interconnects arranged on the second surface of the substrate;
wherein the interconnects include a first quantity of interconnects arranged along a first circular reference line and a second quantity of interconnects arranged along a second circular reference line;
wherein the first and second circular reference lines that are concentric about a radial origin and the first circular reference line is radially outward from the second circular reference line;
wherein the first quantity of interconnects is greater than the second quantity of interconnects;
wherein every interconnect along the first and second circular reference lines includes a minor axis and a major axis greater than its respective minor axis; and
wherein the major axis of every interconnect along the first and second circular reference lines is perpendicular to its respective circular reference line.

12. The apparatus of claim 11 , wherein:
the first quantity of interconnects are uniformly distributed along the first circular reference line; and
the second quantity of interconnects are uniformly distributed along the second circular reference line.

13. The apparatus of claim 11 , wherein a first interconnect of the first quantity of interconnects and a second interconnect of the second quantity of interconnects are further arranged along a first radial reference line that radiates from the radial origin.

14. The apparatus of claim 11 , wherein:
the substrate comprises a semiconductor die; and
first interconnects of the interconnects are connected to circuitry of the semiconductor die.

15. The apparatus of claim 11 , further comprising:
a semiconductor die connected to the first surface of the substrate; and
wherein first interconnects of the interconnects are connected to circuitry of the semiconductor die via the substrate.

16. The apparatus of claim 11 , wherein each interconnect is elliptical.

17. A method comprising:
receiving a substrate having a first surface and a second surface opposite the first surface; and
arranging interconnects on the second surface of the substrate such that the interconnects include at least one of:
first interconnects arranged in each isosceles wedge-shaped region of the second surface bounded by first radial reference lines that radiate from a radial origin of the second surface and form acute central angles at the radial origin, wherein each first interconnect includes a minor axis and a major axis greater than its respective minor axis, and wherein the major axis of each first interconnect in its respective isosceles wedge-shaped region is parallel to a second radial reference line that radiates from the radial origin and bisects the respective isosceles wedge-shaped region; or
second interconnects along circular reference lines that are concentric about the radial origin of the second surface of the substrate, wherein every interconnect along the circular reference lines includes a minor axis and a major axis greater than its respective minor axis; and wherein the major axis of every interconnect along the circular reference lines is perpendicular to its respective circular reference line.

18. The method of claim 17 , wherein arranging the interconnects on the second surface of the substrate comprises arranging the first interconnects in each isosceles wedge-shaped region of the second surface.

19. The method of claim 17 , wherein arranging the interconnects on the second surface of the substrate comprises arranging the second interconnects along the circular reference lines.

20. The method of claim 17 , wherein arranging the interconnects comprises electrically connecting the first interconnects or the second interconnects to circuitry of the substrate.

Assignees

• Amkor Tech Singapore Pte Ltd
• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Rinne Glenn
• Richter Daniel

Classifications

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/237

  Multiple bump connectors having different shapes · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/234

  Cross-sectional shape, i.e. in side view · CPC title