Systems and methods for implementing coherent memory in a multiprocessor system

Patent metadata

Field	Value
Publication number	US-11237969-B2
Application number	US-202016983345-A
Country	US
Kind code	B2
Filing date	Aug 3, 2020
Priority date	Nov 4, 2015
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache locations buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.

First claim

What is claimed is:

1. A multiprocessor system comprising:
a plurality of nodes and at least one memory,
wherein each node contains at least one processor (CPU) and at least one cache private to the node,
a network connecting the nodes,
wherein values of data units stored in the caches are kept coherent by a distributed cache coherence protocol which sends coherence messages on the network,
wherein the network implements a blocking function that blocks some coherence messages from being sent on the network,
wherein sending a coherence message activates the blocking function to block other coherence messages if the other coherence messages are for the same address region as the coherence message.

2. The multiprocessor system of claim 1 , wherein the coherence message is of a broadcast type and is sent to several nodes.

3. The multiprocessor system of claim 1 , wherein one or plural nodes receiving the coherence message each notify the network before the blocking function can be unblocked.

4. The multiprocessor system of claim 1 , wherein a sender of the other coherence message will be notified when the blocking function which the sender has initiated gets unblocked.

5. The multiprocessor system of claim 1 , further comprising:
at least one cache location buffer (CLB) private to each node, wherein each CLB stores information associated with a data unit indicating the identity of the other nodes which contain copies of the data unit in a cache local to those other nodes.

6. The multiprocessor system of claim 5 , wherein the CLBs store location information indicating a location associated with a data unit, wherein each location information can identify a location to be either a location within a private cache in the same node as its CLB, to be in one of the other nodes or to be in memory.

7. The multiprocessor system of claim 5 , wherein the coherence protocol classifies a continuous region of data units to be a private region if the data units only have their respective location information values stored in one or more CLBs which are private to one and the same node.

8. The multiprocessor system of claim 7 , wherein private classification also indicates that only the one and the same node may have any of the region's data units stored in its at least one private caches.

9. The multiprocessor system of claim 7 , wherein at least one CLB entry in the one and the same node stores information associated with the region indicating that it is classified as a private region.

10. The multiprocessor system of claim 1 , further comprising:
at least one cache location buffer (CLB) private to each node, wherein each CLB stores information associated with a data unit indicating the identity of the other nodes containing at least one CLB with location information for the data unit.

11. A method comprising:
storing data units in private caches in nodes of a multiprocessor system and in global caches and a memory, wherein each node contains at least one processor (CPU), at least one cache private to the node;
the nodes being connected via a network;
maintaining coherence of values of data units stored in the caches by a distributed cache coherence protocol which sends coherence messages on the network,
blocking some coherence messages from being sent on the network, and
wherein sending a coherence message activates the blocking function to block other coherence messages if the other coherence messages are for the same address region as the coherence message.

12. The method of claim 11 , wherein the coherence message is of a broadcast type and is sent to several nodes.

13. The method of claim 11 , wherein one or plural nodes receiving the coherence message each notify the network before the blocking function can be unblocked.

14. The method of claim 11 , wherein a sender of the other coherence message will be notified when the blocking function which the sender has initiated gets unblocked.

15. The method of claim 11 , further comprising:
at least one cache location buffer (CLB) private to each node, wherein each CLB stores information associated with a data unit indicating the identity of the other nodes which contain copies of the data unit in a cache local to those other nodes.

16. The method of claim 15 , wherein the CLBs store location information indicating a location associated with a data unit, wherein each location information can identify a location to be either a location within a private cache in the same node as its CLB, to be in one of the other nodes or to be in memory.

17. The method of claim 15 , wherein the coherence protocol classifies a continuous region of data units to be a private region if the data units only have their respective location information values stored in one or more CLBs which are private to one and the same node.

18. The method of claim 17 , wherein private classification also indicates that only the one and the same node may have any of the region's data units stored in its at least one private caches.

19. The method of claim 17 , wherein at least one CLB entry in the one and the same node stores information associated with the region indicating that it is classified as a private region.

20. The method of claim 11 , further comprising:
at least one cache location buffer (CLB) private to each node, wherein each CLB stores information associated with a data unit indicating the identity of the other nodes containing at least one CLB with location information for the data unit.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hagersten Erik
• Sembrant Andreas
• Black-Schaffer David

Classifications

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• G06F2212/1048

  Scalability · CPC title

• G06F12/1441

  for a range · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/1063

  the data cache being concurrently virtually addressed · CPC title