Systems and methods for implementing coherent memory in a multiprocessor system
US-11615026-B2 · Mar 28, 2023 · US
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Black-Schaffer David patents
Black-Schaffer David is listed as an inventor on 18 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Black-Schaffer David |
| Total patents | 18 |
| First publication | Jul 10, 2018 |
| Latest publication | Mar 28, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for implementing coherent memory in a multiprocessor system
US-2022156191-A1 · May 19, 2022 · US
Systems and methods for implementing coherent memory in a multiprocessor system
US-11237969-B2 · Feb 1, 2022 · US
Systems and methods for efficient cacheline handling based on predictions
US-11138121-B2 · Oct 5, 2021 · US
System protecting caches from side-channel attacks
US-10915466-B2 · Feb 9, 2021 · US
Systems and methods for efficient compressed cache line storage and handling
US-10866891-B2 · Dec 15, 2020 · US
Systems and methods for implementing coherent memory in a multiprocessor system
US-2020364144-A1 · Nov 19, 2020 · US
Systems and methods for implementing coherent memory in a multiprocessor system
US-10754777-B2 · Aug 25, 2020 · US
Systems and methods for reducing first level cache energy by eliminating cache address tags
US-10671543-B2 · Jun 2, 2020 · US
Management of shared pipeline resource usage based on level information
US-10409725-B2 · Sep 10, 2019 · US
Recent patents
Latest publications not already listed above.
System protecting caches from side-channel attacks
US-2019272239-A1 · Sep 5, 2019 · US
Systems and methods for direct data access in multi-level cache memory hierarchies
US-10402344-B2 · Sep 3, 2019 · US
Systems and methods for implementing a tag-less shared cache and a larger backing cache
US-10402331-B2 · Sep 3, 2019 · US
Systems and methods for efficient cacheline handling based on predictions
US-2019155736-A1 · May 23, 2019 · US
Systems and methods for efficient compressed cache line storage and handling
US-2019155731-A1 · May 23, 2019 · US
Systems and methods for implementing coherent memory in a multiprocessor system
US-2018329819-A1 · Nov 15, 2018 · US
Tracking alternative cacheline placement locations in a cache hierarchy
US-10031849-B2 · Jul 24, 2018 · US
Placement policy for memory hierarchies
US-10019368-B2 · Jul 10, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Samsung Electronics Co Ltd | 18 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0811 | 18 |
| Y02D10/00 | 14 |
| G06F12/084 | 12 |
| G06F12/0817 | 10 |
| G06F12/0864 | 10 |