Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor

Patent metadata

Field	Value
Publication number	US-9710387-B2
Application number	US-201213359767-A
Country	US
Kind code	B2
Filing date	Jan 27, 2012
Priority date	Jan 27, 2011
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

First claim

What is claimed is:

1. A method for translating instructions for a processor, the method comprising:
accessing a plurality of guest instructions that comprise multiple guest branch instructions;
assembling the plurality of guest instructions into a guest instruction block;
translating the guest instruction block to a corresponding first native conversion block, wherein the guest instruction block comprises instructions of a guest instruction architecture and wherein the corresponding first native conversion block comprises instructions of a native instruction architecture;
accumulating translated native instructions in a native conversion buffer during the translating;
storing the native conversion block into a native cache;
storing a mapping of a guest far branch ending the guest instruction block to a corresponding native instruction in a conversion look aside buffer, wherein the corresponding native instruction is a first instruction in a second native conversion block;
responsive to a subsequent request for the guest far branch, indexing the conversion look aside buffer using a target address of the guest far branch to determine whether a hit occurred, wherein the mapping indicates the guest far branch has the corresponding second native conversion block in the native cache; and
forwarding the second native conversion block for execution responsive to the hit.

2. The method of claim 1 , further comprising using a hardware fetch logic component to fetch the plurality of guest instructions independent of the processor.

3. The method of claim 1 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered mappings of guest instruction blocks to corresponding native conversion blocks stored therein.

4. The method of claim 1 , wherein a conversion buffer code cache is maintained within a system memory and further comprising maintaining cache coherency between the conversion look aside buffer and the conversion buffer code cache.

5. The method of claim 4 , wherein the conversion buffer code cache is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer code cache and the conversion look aside buffer.

6. The method of claim 1 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

7. A system for translating instructions for a processor, the system comprising:
a guest fetch logic component for accessing a plurality of guest instructions that comprise multiple guest branch instructions;
a guest fetch buffer for assembling the plurality of guest instructions into a guest instruction block;
a plurality of conversion tables for translating the guest instruction block into a corresponding native conversion block;
a native conversion buffer for accumulating translated native instructions during the translating;
a native cache for storing the native conversion block;
a conversion look aside buffer for storing a mapping of a guest far branch ending the guest instruction block to a corresponding native instruction in a conversion look aside buffer, wherein the corresponding native instruction is a first instruction in a second native conversion block; and
wherein, upon a subsequent request for the guest far branch, logic for indexing the conversion look aside buffer using a target address of the guest far branch to determine whether a hit occurred, wherein the mapping indicates the guest far branch has the corresponding second native conversion block in the native cache, and logic for forwarding the second native conversion block for execution in response to the hit.

8. The system of claim 7 , wherein the guest fetch logic component is implemented in hardware and fetches the plurality of guest instructions independent of the processor.

9. The system of claim 7 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered mappings stored therein.

10. The system of claim 7 , wherein a conversion buffer code cache is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer code cache.

11. The system of claim 10 , wherein the conversion buffer code cache is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer code cache and the conversion look aside buffer.

12. The system of claim 7 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

13. A microprocessor that implements a method of translating instructions, said microprocessor comprising:
a microprocessor pipeline; and
a hardware accelerator module coupled to the microprocessor pipeline, wherein the hardware accelerator module further comprises:
a guest fetch logic component for accessing a plurality of guest instructions that comprise multiple guest branch instructions;
a guest fetch buffer for assembling the plurality of guest instructions into a guest instruction block;
a plurality of conversion tables for translating the guest instruction block into a corresponding native conversion block;
a native conversion buffer for accumulating translated native instructions during the translating;
a native cache for storing the native conversion block;
a conversion look aside buffer for storing a mapping of a guest far branch ending the guest instruction block to a corresponding native instruction in a conversion look aside buffer, wherein the corresponding native instruction is a first instruction in a second native conversion block; and
wherein, upon a subsequent request for the guest far branch, logic for indexing the conversion look aside buffer using a target address of the guest far branch to determine whether a hit occurred, wherein the mapping indicates the guest far branch has the corresponding second native conversion block in the native cache, and logic for forwarding the second native conversion block for execution in response to the hit.

14. The microprocessor of claim 13 , wherein the guest fetch logic component is implemented in hardware and is operable to fetch the plurality of guest instructions independent of the processor.

15. The microprocessor of claim 13 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered native conversion blocks stored therein.

16. The microprocessor of claim 13 , wherein a conversion buffer code cache is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer code cache.

17. The microprocessor of claim 16 , wherein the conversion buffer code cache is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer code cache and the conversion look aside buffer.

18. The microprocessor of claim 13 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

19. The microprocessor of claim 13 wherein the plurality of guest instructions comprise one of Java, JavaScript, x86, MIPS, and SPARC.

20. The microprocessor of claim 19 wherein the microprocessor is operable to implement a virtual instruction set

Assignees

• Abdallah Mohammad
• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F9/3808

  for instruction reuse, e.g. trace cache, branch target cache · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/30174 Primary

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F2212/151

  Emulated environment, e.g. virtual machine · CPC title