Electrochemical additive manufacturing of interconnection features

Patent metadata

Field	Value
Publication number	US-11232956-B2
Application number	US-202017112909-A
Country	US
Kind code	B2
Filing date	Dec 4, 2020
Priority date	Nov 19, 2015
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

First claim

What is claimed is:

1. A method of electrochemical additive manufacturing of interconnection features each having multiple layers, comprising:
obtaining a plate comprising one or more tiles, each tile of said one or more tiles comprising an electrical circuit, which comprises one or more electrical connection points, wherein said plate further comprises a conductive seed layer;
electrically coupling said conductive seed layer to a power supply;
placing a surface of said conductive seed layer in contact with an electrolyte solution;
placing an anode array in contact with said electrolyte solution, wherein:
said anode array comprises a plurality of deposition anodes; and
each deposition anode of said plurality of deposition anodes is configured to independently provide current that flows from said power supply through said deposition anode to said plate through said electrolyte solution, resulting in deposition of material onto said plate;

aligning said plate and said anode array;
obtaining a build plan that comprises a layer description of each layer of the interconnection features; and
manufacturing each layer of the multiple layers of one or more of the interconnection features, each electrically coupled to a corresponding electrical connection point of said one or more electrical connection points of the electrical circuit of said each tile, wherein said manufacturing said one or more interconnection features comprises controlling an amount of said current that flows from said each deposition anode to deposit said material onto said plate to form said one or more interconnection features, and manufacturing each layer of each one of the one or more interconnection features comprises:
setting or confirming a position of the cathode relative to the anode array to begin the manufacturing of the layer;
transmitting control signals to the anode array based on a layer description of the layer;
measuring one or more feedback signals across the anode array;
analyzing the one or more feedback signals to produce a deposition analysis that comprises an extent to which deposition has progressed at one or more locations within the layer, wherein analyzing the one or feedback signals comprises applying one or more transformations to the feedback signals, wherein the one or more transformations comprise one or more of morphological filters and Boolean operations; and
continuing or completing manufacturing of the layer in response to the deposition analysis,

wherein manufacturing the one or more interconnection features further comprises, while maintaining contact between the anode array and the electrolyte solution, manufacturing a plurality of layers of the one or more interconnection features by depositing the material onto the plate to form a first one of the plurality of layers, having a raw surface, and depositing the material directly onto the raw surface of the first one of the plurality of layers to form a second one of the plurality of layers.

2. The method of claim 1 , wherein said one or more interconnection features comprise one or more wafer bumps.

3. The method of claim 1 , wherein said one or more interconnection features comprise one or more pillars.

4. The method of claim 1 , wherein said aligning said plate and said anode array comprises:
using one or more sensors to determine a three-dimensional position and a three-dimensional orientation of said plate relative to said anode array; and
using one or more actuators to set or modify said three-dimensional position and said three-dimensional orientation of said plate relative to said anode array.

5. The method of claim 1 , further comprising removing portions of said conductive seed layer not covered by said one or more interconnection features.

6. The method of claim 1 , further comprising controlling said amount of said current that flows from said each deposition anode to increase a thickness of said conductive seed layer in one or more regions of said plate.

7. The method of claim 1 , wherein one or more of said one or more interconnection features comprise portions that are not perpendicular to said plate.

8. The method of claim 7 , further comprising successively activating horizontally offset anodes of said plurality of deposition anodes to construct said portions that are not substantially perpendicular to said plate.

9. The method of claim 8 , further comprising:
constructing vertical portions of said one or more of said one or more interconnection features that are substantially perpendicular to said plate;
depositing an inert material onto said plate between said vertical portions; and
activating said horizontally offset anodes after said depositing said inert material.

10. The method of claim 1 , wherein:
said material comprises a first material and a second material; and
said deposit said material onto said plate to form said one or more interconnection features comprises:
deposit said first material onto said plate; and
deposit said second material on top of said first material.

11. The method of claim 10 , wherein:
said first material comprises copper; and
said second material comprises one or more of tin, silver, or lead.

12. The method of claim 1 , wherein:
said plate comprises two or more tiles; and
said manufacturing said one or more interconnection features further comprises using one or more actuators to position said anode array proximal to each tile of said two or more tiles to manufacture interconnection features associated with said each tile.

13. The method of claim 1 , wherein said manufacturing said one or more interconnection features further comprises:
obtaining a build plan that comprises a layer description of each layer of the plurality of layers of said one or more interconnection features, wherein the layer description comprises:
a target map comprising a desired presence or absence of the material at a plurality of locations within an associated layer; and
one or more process parameter values that affect a manufacturing process for the associated layer,

wherein manufacturing each layer of the plurality of layers further comprises:
setting or confirming a position of the plate relative to the anode array to begin the manufacturing of the layer;
transmitting control signals to the anode array based on the layer description of the layer;
measuring one or more feedback signals across the anode array;
analyzing the one or more feedback signals to produce a deposition analysis that comprises an extent to which deposition has progressed at the plurality of locations within the layer;
determining whether deposition of the layer is complete based on the deposition analysis;
when deposition of the layer is not complete, determining whether to modify one or more of the one or more process parameter values associated with the layer; and
when deposition of the layer is complete and when a subsequent layer of the plurality of layers has not been manufactured, manufacturing the subsequent layer.

14. The method of claim 13 , wherein the one or more feedback signals comprise a map of current across the anode array.

15. The system of claim 13 , wherein manufacturing a layer of the plurality of layers further comprises calculating a map of desired current output from each deposition anode of the anode array that will generate deposition that corresponds to the target map associated with the layer.

16. The method of claim 15 , wherein calculating the map of desired current output from each deposition anode comprises applying one or more transformations to the target map

Assignees

• Fabric8Labs Inc

Inventors

• Pain David
• Edmonds Andrew
• Herman Jeffrey
• Pateros Charles
• Shaik Kareemullah

Classifications

• H10W70/041

  Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps · CPC title

• H10W40/037

  Assembling together parts thereof · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/237

  Multiple bump connectors having different shapes · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title