Three dimensional integrated circuit electrostatic discharge protection and prevention test interface

Patent metadata

Field	Value
Publication number	US-11229109-B2
Application number	US-202016851873-A
Country	US
Kind code	B2
Filing date	Apr 17, 2020
Priority date	Dec 17, 2012
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.

First claim

We claim:

1. A probe card assembly comprising:
a probe card printed circuit board (PCB);
a probe card substrate adjacent the probe card PCB;
a probe card head adjacent the probe card substrate and opposite the PCB; and
a plurality of probe card pins connected to the probe card head,
wherein when the probe card pins couple probe pads on a device under test (DUT), voltage is forced on ones of a plurality of input/output channels connected to the probe card assembly to dissipate charges resident on the DUT to provide electrostatic discharge protection.

2. The probe card assembly of claim 1 , wherein the forced channel is selected from the group consisting of a ground channel having resistance and a power channel having resistance.

3. The probe card assembly of claim 1 , wherein DUT comprises a wafer.

4. The probe card assembly of claim 1 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

5. The probe card assembly of claim 4 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

6. The probe card assembly of claim 1 , wherein when the probe card pins couple probe pads on the wafer, the first voltage is applied on at least one of the plurality of input/output channels and a second voltage is then applied on the at least one of the plurality of input/output channels so as to dissipate charges resident on the DUT to provide electrostatic discharge protection.

7. The probe card assembly of claim 6 , wherein the first and second voltages are with a same magnitude but different signs.

8. The probe card assembly of claim 1 , wherein the PCB is a grounding PCB, and the probe card substrate includes a conductive material and can mate with any type of probe card head.

9. The probe card assembly of claim 8 , wherein the grounding PCB includes routing circuitry to short all signal traces to ground traces to disperse electrostatic discharge current.

10. A probe card assembly comprising:
a probe card printed circuit board (PCB);
a probe card substrate adjacent the probe card PCB;
a probe card head adjacent the probe card substrate and opposite the PCB; and
a plurality of probe card pins connected to the probe card head,
wherein when the probe card pins couple probe pads on a device under test (DUT), two voltages with a same magnitude but different signs are sequentially applied on at least one of the plurality of input/output channels to dissipate charges resident on the DUT to provide electrostatic discharge protection.

11. The probe card assembly of claim 10 , wherein the forced channel is selected from the group consisting of a ground channel having resistance and a power channel having resistance.

12. The probe card assembly of claim 10 , wherein the DUT comprises a wafer.

13. The probe card assembly of claim 10 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

14. The probe card assembly of claim 13 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

15. The probe card assembly of claim 10 , wherein the PCB is a grounding PCB, and the probe card substrate includes a conductive material and can mate with any type of probe card head.

16. The probe card assembly of claim 15 , wherein the grounding PCB includes routing circuitry to short all signal traces to ground traces to disperse electrostatic discharge current.

17. A probe card assembly comprising:
a grounding printed circuit board (PCB) electrically connected to a plurality of input/output channels;
a probe card substrate adjacent the grounding PCB;
a probe card head adjacent the probe card substrate and opposite the grounding PCB; and
a plurality of probe card pins connected to the probe card head,
wherein the plurality of probe card pins are configured to couple a device under test (DUT), and wherein when the plurality of probe card pins couple the DUT, voltage is forced on ones of the plurality of input/output channels to dissipate charges resident on the wafer to provide electrostatic discharge protection.

18. The probe card assembly of claim 17 , wherein the probe card substrate includes a conductive material selected from the group consisting of nickel alloys, copper alloys, aluminum, and combinations thereof.

19. The probe card assembly of claim 17 , wherein the grounding PCB includes routing circuitry to short all signal traces to ground traces to disperse electrostatic discharge current.

20. The probe card assembly of claim 17 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Mill-Jer
• Peng Ching-Nen
• Lin Hung-Chih
• Cheng Hao

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• G01R1/36

  Overload-protection arrangements or circuits for electric measuring instruments · CPC title

• H05F3/02 Primary

  by means of earthing connections · CPC title

• H05K1/11

  Printed elements for providing electric connections to or between printed circuits · CPC title