Three dimensional integrated circuit electrostatic discharge protection and prevention test interface

Patent metadata

Field	Value
Publication number	US-10652987-B2
Application number	US-201815882256-A
Country	US
Kind code	B2
Filing date	Jan 29, 2018
Priority date	Dec 17, 2012
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.

First claim

We claim:

1. A system to provide electrostatic discharge protection to a wafer comprising:
a probe card assembly electrically connected to a plurality of input/output channels, the probe card assembly comprising:
a probe card printed circuit board (PCB),
a probe card substrate adjacent the probe card PCB,
a probe card head adjacent the probe card substrate and opposite the PCB, and
a plurality of probe card pins connected to the probe card head; and
a secondary assembly comprising an interposer electrically coupled to one or more wafers, each wafer comprising at least a device under test,
wherein when the probe card pins couple probe pads on the wafer, voltage is forced on ones of the plurality of input/output channels to dissipate charges resident on the wafer to provide electrostatic discharge protection.

2. The system of claim 1 , wherein the forced channel is selected from the group consisting of a ground channel having resistance and a power channel having resistance.

3. The system of claim 1 , wherein the secondary assembly further comprises an array of control collapse chip connection bumps connected to respective through silicon vias which are electrically connected to an array of μbumps, the μbumps adaptable to provide an electrical connection between the probe card assembly and the devices under test.

4. The system of claim 1 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

5. The system of claim 4 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

6. The system of claim 1 , wherein when the probe card pins couple probe pads on the wafer, first voltage is applied on at least one of the plurality of input/output channels and second voltage is then applied on the at least one of the plurality of input/output channels so as to dissipate charges resident on the wafer to provide electrostatic discharge protection.

7. The system of claim 6 , wherein the first and second voltages are with a same magnitude but different signs.

8. The system of claim 1 , wherein the PCB is a grounding PCB, and the probe card substrate includes a conductive material and can mate with any type of probe card head.

9. The system of claim 8 , wherein the grounding PCB includes routing circuitry to short all signal traces to ground traces to disperse electrostatic discharge current.

10. A system to provide electrostatic discharge protection to a wafer comprising:
a probe card assembly electrically connected to a plurality of input/output channels, the probe card assembly comprising:
a probe card printed circuit board (PCB),
a probe card substrate adjacent the probe card PCB,
a probe card head adjacent the probe card substrate and opposite the PCB, and
a plurality of probe card pins connected to the probe card head; and
a secondary assembly comprising an interposer electrically coupled to one or more wafers, each wafer comprising at least a device under test,
wherein when the probe card pins couple probe pads on the wafer, two voltages with a same magnitude but different signs are sequentially applied on at least one of the plurality of input/output channels to dissipate charges resident on the wafer to provide electrostatic discharge protection.

11. The system of claim 10 , wherein the forced channel is selected from the group consisting of a ground channel having resistance and a power channel having resistance.

12. The system of claim 10 , wherein the secondary assembly further comprises an array of control collapse chip connection bumps connected to respective through silicon vias which are electrically connected to an array of μbumps, the μbumps adaptable to provide an electrical connection between the probe card assembly and the devices under test.

13. The system of claim 10 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

14. The system of claim 13 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

15. The system of claim 10 , wherein the PCB is a grounding PCB, and the probe card substrate includes a conductive material and can mate with any type of probe card head.

16. The system of claim 15 , wherein the grounding PCB includes routing circuitry to short all signal traces to ground traces to disperse electrostatic discharge current.

17. A probe card assembly comprising:
a grounding printed circuit board (PCB) electrically connected to a plurality of input/output channels;
a probe card substrate adjacent the grounding PCB;
a probe card head adjacent the probe card substrate and opposite the grounding PCB; and
a plurality of probe card pins connected to the probe card head,
wherein the plurality of probe card pins are configured to couple a wafer comprising at least a device under test, and wherein when the plurality of probe card pins couple the wafer, voltage is forced on ones of the plurality of input/output channels to dissipate charges resident on the wafer to provide electrostatic discharge protection, and
wherein the probe card substrate includes a conductive material and can mate with any type of probe card head.

18. The probe card assembly of claim 17 , wherein the conductive material is selected from the group consisting of nickel alloys, copper alloys, aluminum, and combinations thereof.

19. The probe card assembly of claim 17 , wherein the grounding PCB includes routing circuitry to short all signal traces to ground traces to disperse electrostatic discharge current.

20. The probe card assembly of claim 17 , wherein the probe card head further comprises a metal layer thereon for shielding the wafer from charges on the probe card PCB thereby avoiding inducement of charges on the wafer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Mill-Jer
• Peng Ching-Nen
• Lin Hung-Chih
• Cheng Hao

Classifications

• G01R1/07378

  using an intermediate adapter, e.g. space transformers (G01R1/07371 takes precedence) · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H05K1/11

  Printed elements for providing electric connections to or between printed circuits · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• G01R1/36

  Overload-protection arrangements or circuits for electric measuring instruments · CPC title