Planar resistive random-access memory (RRAM) device with a shared top electrode

Patent metadata

Field	Value
Publication number	US-11227997-B1
Application number	US-202016922049-A
Country	US
Kind code	B1
Filing date	Jul 7, 2020
Priority date	Jul 7, 2020
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

Embodiments of the present invention are directed to forming a planar Resistive Random Access Memory (RRAM) device with a shared top electrode. In a non-limiting embodiment of the invention, a first trench having a first width and a second trench having a second width less than the first width are formed in a dielectric layer. A bottom liner is formed on sidewalls of the first trench. The bottom liner pinches off the second trench. A top liner is formed on sidewalls of the bottom liner in the first trench. The top liner is formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed. The exposed portion of the bottom liner is removed, and a memory cell material is formed in the first trench.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a first trench having a first width and a second trench having a second width less than the first width in a dielectric layer;
forming a bottom liner on sidewalls of the first trench, the bottom liner pinching off the second trench;
forming a top liner on sidewalls of the bottom liner in the first trench, the top liner formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed;
removing the exposed portion of the bottom liner; and
forming a memory cell material in the first trench.

2. The method of claim 1 , wherein the top liner does not fill the second trench due to pinch off.

3. The method of claim 2 , wherein an air gap is formed between the top liner and the bottom liner in the second trench.

4. The method of claim 1 , wherein the first width is more than 10 nm and the second width is less than 10 nm.

5. The method of claim 1 , wherein removing the exposed portion of the bottom liner comprises etching the bottom liner selectively to the top liner.

6. The method of claim 5 , wherein the top liner comprises a conductive material having etch selectivity with respect to a wet etch chemistry used to remove the exposed portion of the bottom liner.

7. The method of claim 6 , wherein the bottom liner comprises TiN and the top liner comprises TaN or Ru.

8. The method of claim 6 , wherein the bottom liner comprises TaN and the top liner comprises TiN or Ru.

9. The method of claim 1 , wherein the memory cell material comprises one or more of CuO x , NiO x , CoO x , ZnO x , CrO x , TiO x , HfO x , ZrO, FeO x and NbO x .

10. The method of claim 1 , further comprising forming a bottom electrode contact electrically coupled to a pinched off portion of the bottom liner.

11. The method of claim 10 , further comprising forming a shared top electrode contact electrically coupled to the top liner.

12. The method of claim 1 , wherein forming the bottom liner comprises conformally depositing the bottom liner on the sidewalls of the first trench.

13. The method of claim 11 , wherein forming the top liner comprises non-conformally depositing the top liner on the bottom liner.

14. The method of claim 1 , further comprising forming one or more isolation trenches in a direction orthogonal to the first trench and the second trench to define one or more Resistive Random Access Memory (RRAM) cells.

Assignees

• IBM

Inventors

• Dutta Ashim
• Sharma Saumya
• Zhou Tianji
• Yang Chih-Chao

Classifications

• H01L27/2463

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L45/1691 Primary

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic