Layered cross-point semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9985205-B2
Application number	US-201615061328-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Sep 10, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer. The first interconnect layer includes a first surrounding region and a first extended region. The second interconnect part includes a second core part, and a second interconnect layer. The second interconnect layer includes a second surrounding region and a second extended region. The second extended connection part overlaps a part of the first extended region in the third direction, overlaps the second core part in the first direction, and is electrically connected to the second core part. The second extended surrounding part is provided around the second extended connection part and contains a material contained in the first surrounding region.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first interconnect part;
a second interconnect part separated from the first interconnect part in a first direction;
a metal containing layer; and
a second interconnect connection part overlapping a part of the second interconnect part in the first direction, wherein
the first interconnect part includes
a first core part, and
a first interconnect layer including
a first surrounding region provided around the first core part, and
a first extended region connected to the first surrounding region and extending in a second direction crossing the first direction,

the second interconnect part includes
a second core part, and
a second interconnect layer including
a second surrounding region provided around the second core part,
a first surface facing the second core part,
a second surface separated from the first surface, and
a second extended region connected to the second surrounding region and extending in a third direction crossing the first direction and the second direction,

the second interconnect connection part includes
a second extended connection part overlapping a part of the first extended region in the third direction, overlapping the second core part in the first direction, and electrically connected to the second core part, and
a second extended surrounding part provided around the second extended connection part and containing a material contained in the first surrounding region,

the metal containing layer is provided between the second extended surrounding part and the second surrounding region and between the second extended region and the first interconnect layer, and
the metal containing layer is disposed on the second surface of the second interconnect layer.

2. The device according to claim 1 , further comprising a first resistance change layer provided between the second extended region and the first extended region and between the second surrounding region and the second extended surrounding part.

3. The device according to claim 1 , further comprising:
a first conductive part provided to be separated from the first core part;
a first conductive connection part provided between the first conductive part and the first core part;
a second conductive part provided to be separated from the second extended connection part; and
a second conductive connection part provided between the second conductive part and the second extended connection part.

4. The device according to claim 3 , further comprising a first metal boundary layer provided between the first surrounding region and the first connection part and between the first core part and the first conductive connection part.

5. The device according to claim 3 , further comprising:
a first layer second metal boundary layer provided between the second extended surrounding part and the second extended connection part and between the second extended connection part and the second conductive connection part; and
a second layer second metal boundary layer provided between the second surrounding region and the second core part and between the second core part and the second extended connection part.

6. The device according to claim 1 , wherein
the first surrounding region is provided around the first core part,
the second surrounding region is provided around the second core part, and
the second extended surrounding part is provided around the second extended connection part.

7. The device according to claim 1 , further comprising:
a third core part separated from the first core part and separated from the second core part;
a third interconnect layer including a third surrounding region provided around the third core part, and a third extended region provided to be separated from the second extended region in the first direction, connected to the third surrounding region and extending in the second direction;
a third extended connection part overlapping the third core part in the first direction;
a third extended surrounding part provided around the third extended connection part and containing the material contained in the first surrounding region;
a third extended intermediate connection part provided between the third core part and the third extended connection part, electrically connected to the third core part and electrically connected to the third extended connection part; and
a third extended intermediate surrounding part provided around the third extended intermediate connection part and containing a material contained in the second surrounding region.

8. The device according to claim 7 , further comprising: a second resistance change layer provided between the third surrounding region and the third extended intermediate surrounding part and between the third interconnect layer and the second interconnect layer.

9. The device according to claim 7 , further comprising:
a third conductive part provided to be separated from the third core part; and
a third conductive connection part provided between the third conductive part and the third core part.

10. The device according to claim 9 , further comprising:
a first layer third metal boundary layer provided between the third extended surrounding part and the third extended connection part and between a third extended connection part and the third interconnect connection part;
a second layer third metal boundary layer provided between the third extended intermediate surrounding part and the third extended intermediate connection part and between the third extended intermediate connection part and the third extended connection part; and
a third layer third metal boundary layer provided between the third surrounding region and the third core part and between the third core part and the third extended intermediate connection part.

11. The device according to claim 7 , wherein
the third surrounding region is provided around the third core part;
the third extended surrounding part is provided around the third extended connection part; and
the third extended intermediate surrounding part is provided around the third extended intermediate connection part.

Assignees

• Toshiba Memory Corp

Inventors

• Arayashiki Yusuke

Classifications

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H01L45/1253

  Electricity · mapped topic

• H01L45/148

  Electricity · mapped topic

• H01L45/1266

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic