Semiconductor device

Patent metadata

Field	Value
Publication number	US-11227647-B2
Application number	US-202017106242-A
Country	US
Kind code	B2
Filing date	Nov 30, 2020
Priority date	Oct 19, 2018
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

A semiconductor device is provided. The semiconductor device includes: a processor core which processes program data; a first memory mounted on the same semiconductor chip as the processor core; a second memory including an MRAM cell having a first MTJ (Magnetic Tunnel Junction) structure; a third memory including an MRAM cell having a second MTJ structure different from the first MTJ structure, wherein the processor core selectively stores the program data in one of the first memory, the second memory and the third memory, on the basis of an attribute of the program data.

First claim

What is claimed is:

1. A semiconductor device comprising:
a processor core configured to process program data;
a first memory including a first MTJ structure; and
a second memory including a second MTJ structure having a height different from the first MTJ structure,
wherein the processor core is further configured to read first data stored in the first memory, generate second data on the basis of the first data, store the second data in the second memory, and execute a program operation using the first data and the second data.

2. The semiconductor device of claim 1 ,
wherein the second MTJ structure has a height higher than the first MTJ structure, and
wherein the processor core is configured to generate the second data while the program operation is executing, and delete the second data from the second memory after the program operation is executed.

3. The semiconductor device of claim 1 , further comprising:
an SRAM configured to store third data to be processed by the processor core,
wherein the processor core is further configured to generate the third data based on the first data, store the third data in the SRAM, and execute the program operation using the first data, the second data, and the third data.

4. The semiconductor device of claim 3 ,
wherein the second MTJ structure has a height higher than the first MTJ structure, and
wherein the processor core is further configured to delete each of the second data and the third data from the second memory and the SRAM, respectively, after the program operation is executed.

5. The semiconductor device of claim 3 ,
wherein the attribute of the first data is RO (Read Only) data, and the attribute of the second data and third data is RW (Read/Write) data.

6. The semiconductor device of claim 5 ,
wherein the attribute of the second data is RI (Read Intensive) data, and the attribute of third data is WI (Write Intensive) data.

7. The semiconductor device of claim 3 , wherein the attribute of the first data is code data, the attribute of the second data is heap data and the attribute of the third data is stack data.

8. The semiconductor device of claim 1 ,
wherein each of the first MTJ structure and the second MTJ structure includes a pinned layer, a tunnel layer, and a free layer, and
wherein the first MTJ structure and the second MTJ structure are formed so that at least one of a cross-sectional area, a thickness of the tunnel layer, and a thickness of the free layer differs between the first MTJ structure and the second MTJ structure.

9. The semiconductor device of claim 8 , wherein a cross-sectional area of the second MTJ structure is formed to be larger than a cross-sectional area of the first MTJ structure.

10. The semiconductor device of claim 8 , wherein a thickness of the tunnel layer of the second MTJ structure is formed to be larger than a thickness of the tunnel layer of the first MTJ structure.

11. The semiconductor device of claim 8 , wherein a thickness of the free layer of the second MTJ structure is formed to be larger than a thickness of the free layer of the first MTJ structure.

12. A semiconductor device comprising:
a processor core mounted on a first semiconductor chip and configured to execute a program operation;
a first memory mounted on the first semiconductor chip and configured to store data used for the program operation;
a second memory mounted on the first semiconductor chip and having a first MTJ structure different from a memory cell included in the first memory; and
a third memory mounted on the first semiconductor chip and including a second MTJ structure having a height different from the first MTJ structure,
wherein the processor core is further configured to selectively determine a memory in which data is stored based on a range of a virtual address region allocated to data used for the program operation.

13. The semiconductor device of claim 12 ,
wherein the processor core is further configured to allocate a first address range, a second address range, and a third address range, in an order of previously generated data, among data used in the program operation, and
wherein the processor core is further configured to store data included in the second address range in the first memory, and to selectively stores data, which are included in the first address range and the third address range, in the second memory or the third memory.

14. The semiconductor device of claim 12 ,
wherein the processor core is further configured to allocate a first address range for storing a code of the program operation, a second address range for storing a local variable defined in the program operation, and a third address range dynamically allocated for a dynamic variable in the program operation,
the processor core is further configured to store first data, which is included in the first address range, in the second memory, generate second data included in the second address range and third data included in the third address range based on the first data, store the second data in the first memory, store the third data in the third memory, and execute the program operation, using the first data, the second data, and the third data.

15. The semiconductor device of claim 14 , wherein the attribute of the first data is RO (Read Only) data, and the attribute of the second data, the attribute of the second data is WI (Write Intensive) data, and the attribute of the third data is RI (Read Intensive) data.

16. The semiconductor device of claim 12 , wherein the first memory is a static random access memory (SRAM).

17. The semiconductor device of claim 16 , wherein the second MTJ structure has a height higher than the first MTJ structure.

18. A semiconductor device comprising:
a processor core mounted on a semiconductor chip and configured to process program data;
a first memory mounted on the semiconductor chip;
a second memory including a magneto-resistive random access memory (MRAM) cell having a first Magnetic Tunnel Junction (MTJ) structure; and
a third memory including an MRAM cell having a second MTJ structure different from the first MTJ structure,
wherein the processor core determines an attribute of the program data based on an order stored in a memory, among a plurality of program data required when executing one program operation, and
wherein the processor core sequentially stores the program data in the second memory, the first memory, and the third memory in accordance with the order stored in the memory.

19. The semiconductor device of claim 18 ,
wherein each of the first MTJ structure and the second MTJ structure includes a pinned layer, a tunnel layer, and a free layer, and
wherein the first MTJ structure and the second MTJ structure are formed so that the second MTJ structure is formed to be larger than the first MTJ structure in at least one of a cross-sectional area, a thickness of the tunnel layer, and a thickness of the free layer.

20. The semiconductor device of claim 18 , wherein the second memory and the third memory are mounted on the semiconductor chip with the first memory.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sang Kil

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C17/02

  using magnetic or inductive elements (G11C17/14 takes precedence) · CPC title

• G11C11/1677 Primary

  Verifying circuits or methods · CPC title

• G06F16/258

  Data format conversion from or to a database · CPC title

• G06F16/00

  Information retrieval; Database structures therefor; File system structures therefor · CPC title