Data relocation in hybrid memory

Patent metadata

Field	Value
Publication number	US-10649665-B2
Application number	US-201615345919-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 8, 2016
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory, wherein the memory includes a first type of memory and a second type of memory; and
a controller configured to:
identify a subset of data stored in the first type of memory to relocate to the second type of memory upon determining an address corresponding to the subset of data stored in the first type of memory has been accessed least frequently during program operations performed on the memory;
set a threshold amount of data for determining whether to relocate data stored in the second type of memory to the first type of memory;
identify a subset of data stored in the second type of memory to relocate to the first type of memory upon determining an amount of data sensed during a sense operation performed on the subset of data stored in the second type of memory does not meet the threshold amount of data; and
initiate a relocation of the identified subset of data stored in the second type of memory from the second type of memory to the first type of memory upon determining the amount of data sensed during the sense operation does not meet the threshold amount of data.

2. The apparatus of claim 1 , wherein the controller is configured to identify the subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a position of the subset of data in a first in, first out (FIFO) buffer in the first type of memory.

3. The apparatus of claim 1 , wherein the controller is configured to identify the subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on whether the subset of data is in a first in, first out (FIFO) buffer in the first type of memory.

4. The apparatus of claim 1 , wherein data indicating the frequency at which the address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory is included in the first type of memory.

5. The apparatus of claim 4 , wherein the controller is configured to periodically update the data indicating the frequency at which the address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.

6. The apparatus of claim 4 , wherein the controller is configured to update the data indicating the frequency at which the address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory upon the subset of data being accessed during a program operation performed on the memory.

7. An apparatus, comprising:
a memory, wherein the memory includes a first type of memory and a second type of memory; and
a controller configured to:
set a threshold amount of data for determining whether to relocate data stored in the first type of memory to the second type of memory;
identify a subset of data stored in the first type of memory to relocate to the second type of memory upon determining an amount of data sensed during a sense operation performed on the subset of data stored in the first type of memory does not meet the threshold amount of data;
initiate a relocation of the identified subset of data stored in the first type of memory from the first type of memory to the second type of memory upon determining the amount of data sensed during the sense operation does not meet the threshold amount of data; and
identify a subset of data stored in the second type of memory to relocate to the first type of memory upon determining an address corresponding to the subset of data stored in the first type of memory has been accessed least frequently during program operations performed on the memory.

8. The apparatus of claim 7 , wherein the second type of memory is 3D XPoint memory.

9. The apparatus of claim 7 , wherein the second type of memory is resistance variable memory.

10. The apparatus of claim 7 , wherein the controller is configured to identify the subset of data stored in the first type of memory to relocate to the second type of memory upon the sense operation being performed on the subset of data stored in the first type of memory.

11. A method for operating memory, comprising:
identifying a first subset of data among a number of subsets of data to relocate to a second type of memory upon determining that the first subset of data has been accessed least frequently during program operations performed on the memory, wherein the number of subsets of data are stored in a first type of memory;
setting a threshold amount of data for determining whether to relocate data stored in the second type of memory to the first type of memory;
identifying a second subset of data among a number of subsets of data stored in the second type of memory to relocate to the first type of memory upon determining an amount of data sensed during a sense operation performed on the second subset of data stored in the second type of memory does not meet or exceed the threshold amount of data;
relocating the first identified subset of data from the first type of memory to the second type of memory; and
relocating the second identified subset of data from the second type of memory to the first type of memory upon determining the amount of data sensed during the sense operation does not meet or exceed the threshold amount of data.

12. The method of claim 11 , wherein the first subset of data that has been accessed least frequently during program operations performed on the memory is an oldest subset of data in a first in, first out (FIFO) buffer in the first type of memory.

13. The method of claim 11 , wherein the first subset of data that has been accessed least frequently during program operations performed on the memory is a subset of data that has been removed from a first in, first out (FIFO) buffer in the first type of memory.

14. The method of claim 11 , wherein:
the first type of memory includes a number of first in, first out (FIFO) buffers, wherein:
a first one of the number of FIFO buffers includes subsets of data stored in the first type of memory that have been relocated from the second type of memory to the first type of memory and have not been accessed during program operations performed on the memory subsequent to being relocated;
a second one of the number of FIFO buffers includes subsets of data stored in the first type of memory that have been accessed once during program operations performed on the memory;
a third one of the number of FIFO buffers includes subsets of data stored in the first type of memory that have been accessed twice during program operations performed on the memory; and
a fourth one of the number of FIFO buffers includes subsets of data stored in the first type of memory that have been accessed three or more times during program operations performed on the memory; and

the first subset of data that has been accessed least frequently during program operations performed on the memory is a subset of data that has been removed from either the first one of the number of FIFO buffers or the second one of the number of FIFO buffers.

15. The method of claim 14 , wherein the method includes:
updating data for a respective one of the number of subsets of data stored in the first type of memory indicating a frequency at which an address corresponding to that respective subset of data has been accessed during program operations performed on the memory if that respective subset of data has been removed from either the third one of the number of FIFO buffers or the fourth on

Assignees

• Micron Technology Inc

Inventors

• Confalonieri Emanuele
• Dallabora Marco
• Amato Paolo
• Caraccio Danilo
• Balluchi Daniele

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F3/068

  Hybrid storage device · CPC title

• G06F3/0649

  Lifecycle management · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title