Analog-to-digital converting apparatuses and operating methods

Patent metadata

Field	Value
Publication number	US-11223367-B2
Application number	US-202017027874-A
Country	US
Kind code	B2
Filing date	Sep 22, 2020
Priority date	Feb 6, 2020
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

An analog-to-digital converting apparatus includes a first stage converter which performs a first analog-to-digital conversion on an input analog signal during a first stage period, a second stage converter which receives a first residue from the first stage converter amplified by a first gain and which performs a second analog-to-digital conversion during a second stage period, and a recombination logic circuit which combines a first output signal from the first stage converter and a second output signal from the second stage converter into an output digital signal that corresponds to the input analog signal. The second stage converter generates a second stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second stage period, and generates a second output signal of a second sub-cycle subsequent to the first sub-cycle based on the second stage feedback signal.

First claim

What is claimed is:

1. An analog-to-digital converting apparatus comprising:
a first stage converter configured to perform a first analog-to-digital conversion on an input analog signal during a first stage period, and configured to output a first output signal and a first residue;
a first transmission circuit connected to an output terminal of the first stage converter and configured to output the first residue amplified by a first gain;
a plurality of second stage converters each configured to receive the first residue amplified by the first gain, configured to perform a second analog-to-digital conversion during a second stage period, and configured to output a second output signal;
a plurality of first switches configured to switch according to an enable signal, each of the plurality of the first switches connected to at least two second stage converters of the plurality of second stage converters; and
a recombination logic circuit configured to combine the first output signal and the second output signal, and configured to output an output digital signal that corresponds to the input analog signal,
wherein each second stage converter is configured to generate a second stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second stage period, and is configured to generate a second output signal of a second sub-cycle subsequent to the first sub-cycle based on the second stage feedback signal, and
wherein the enable signal enables each of the second stage converters in a time interleaved manner.

2. The analog-to-digital converting apparatus of claim 1 , wherein each second stage converter comprises:
a second transmission circuit connected between an input terminal of the second stage converter and an output terminal of the second stage converter, and configured to output the second stage feedback signal obtained by amplifying the second output signal by the first gain to the input terminal of the second stage converter; and
a second switch which is turned on according to an inverted enable signal opposite to the enable signal.

3. The analog-to-digital converting apparatus of claim 2 , wherein the first transmission circuit and the second transmission circuit each comprise a source follower circuit.

4. The analog-to-digital converting apparatus of claim 1 , wherein the enable signal is at an off value during the first stage period and is at an on value when the second stage period starts.

5. The analog-to-digital converting apparatus of claim 1 , wherein the first stage converter is a successive approximation register converter (SAR ADC), and wherein the first stage converter comprises:
a sample-and-hold circuit configured to sample the input analog signal according to a sampling signal;
a comparator configured to compare the sampled input analog signal based on a first stage feedback signal to output the first residue and a pre-output signal;
a SAR logic circuit configured to count the pre-output signal to generate the first output signal; and
a SAR DAC (Digital Analog Converter) configured to convert the first output signal within the first stage period to generate a first stage feedback signal.

6. The analog-to-digital converting apparatus of claim 1 , wherein each second stage converter is a delta sigma (DS) converter, and wherein each second stage converter comprises:
a loop filter circuit configured to filter a signal obtained by combining the amplified first residue and the amplified second stage feedback signal;
a quantization circuit configured to digitally convert an output signal of the loop filter circuit;
a DS logic circuit configured to count an output of the quantization circuit to generate the second output signal; and
a DS DAC (Digital to Analog) configured to convert the output of the quantization circuit to output the second stage feedback signal.

7. A wireless communication device comprising the analog-to-digital converting apparatus of claim 1 , the wireless communication device further comprising:
a low noise amplifier configured to amplify a radio frequency (RF) signal received through an antenna;
a mixer configured to down-convert the amplified RF signal to a baseband frequency range;
a low pass filter configured to filter the signal down-converted by the mixer; and
a digital signal processor configured to process the output digital signal;
wherein the analog-to-digital converting apparatus is configured to receive the input analog signal from the low pass filter and configured to convert the input analog signal into the output digital signal.

8. An analog-to-digital converting apparatus comprising:
a successive approximation register (SAR) converter configured to perform a first analog-to-digital signal conversion on an input analog signal during a first time period, and configured to output a first output signal and a first residue;
a first transmission circuit configured to amplify the first residue by a first gain;
a plurality of delta-sigma (DS) converters each configured to perform a second analog-to-digital conversion based on the amplified first residue based on a DS feedback signal during a second time period, and each configured to generate a respective second output signal, wherein each DS converter of the plurality of DS converters comprises a second transmission circuit configured to amplify the second output signal by the first gain to generate the DS feedback signal;
a plurality of first switches connected between the transmission circuit and a respective DS converter of the plurality of DS converters, each first switch configured to be controlled by an enable signal, and each first switch configured to transmit the amplified first residue to the respective DS converter in a time interleaved manner; and
a recombination logic circuit configured to combine the first output signal and the second output signals generated by the plurality of DS converters to output an output digital signal.

9. The analog-to-digital converting apparatus of claim 8 , wherein each of the plurality of DS converters further comprises a second switch connected between the second transmission circuit of the DS converter and an input terminal of the DS converter and enabled according to an inverted enable signal.

10. The analog-to-digital converting apparatus of claim 9 , wherein each of the plurality of DS converters comprises:
a loop filter circuit configured to filter a signal obtained by combining the first residue and the DS feedback signal;
a quantization circuit configured to perform a digital conversion on an output signal of the loop filter circuit;
a DS logic circuit configured to count an output of the quantization circuit to generate the second output signal; and
a Delta-Sigma Digital to Analog converter (DS DAC) configured to perform an analog conversion on an output of the quantization circuit to output the DS feedback signal.

11. The analog-to-digital converting apparatus of claim 8 , wherein the enable signal is a signal set to an on value after the first period and before the second period.

12. The analog-to-digital converting apparatus of claim 8 , wherein the first transmission circuit and the second transmission circuits are identical.

13. The analog-to-digital converting apparatus of claim 8 , wherein the SAR converter comprises:
a sample-and-hold circuit configured to receive and sample the input analog signal;
a comparator configured to compare the sampled input analog signal based on a SAR feedback signal to output the first residue and a pre-output signal;
a SAR logic circuit configured to count the pre-output signal

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Il Hoon
• Roh Hyung Dong
• Baek Seung Yeob
• Choi Michael

Classifications

• H04B1/123

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title