Analog-to-digital converters for successive approximation incorporating delta sigma analog-to-digital converters and hybrid digital-to-analog with charge-sharing and charge redistribution

Patent metadata

Field	Value
Publication number	US-9654130-B2
Application number	US-201615210308-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	Jul 8, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.

First claim

What is claimed is:

1. An analog-to-digital converter comprising:
a sample and hold circuit configured to sample an analog input signal to generate a plurality of bits;
a first analog-to-digital converter configured to generate a first digital signal based on the analog input signal, comprising
a charge-sharing digital-to-analog converter configured to convert a first most-significant-bit of the plurality of bits, and
a charge redistribution digital-to-analog converter configured to convert a first least significant bit of the plurality of bits,
wherein the first digital signal is generated based on an output of the charge-sharing digital-to-analog converter and an output of the charge redistribution digital-to-analog converter;

a second analog-to-digital converter configured to generate a second digital signal based on an output of the first analog-to-digital converter, wherein the second analog-to-digital converter comprises a delta sigma digital-to-analog converter, wherein the delta sigma digital-to-analog converter is configured to convert a second least significant bit of the plurality of bits, wherein the second digital signal is generated based on an output of the delta sigma digital-to-analog converter, and wherein the second analog-to-digital converter is a fine conversion analog-to-digital converter relative to the first analog-to-digital converter; and
a combination circuit configured to combine the first digital signal and the second digital signal to provide a resultant output signal.

2. The analog-to-digital converter of claim 1 , wherein:
the first analog-to-digital converter comprises a control module;
the control module is configured to perform successive approximations based on the plurality of bits to generate the first digital signal;
the second analog-to-digital converter comprises a decimation filter; and
the decimation filter is configured to suppress noise and output the second digital signal.

3. The analog-to-digital converter of claim 1 , wherein:
the charge-sharing digital-to-analog converter is configured to (i) receive a digital input signal having an input voltage, and (ii) convert the first most-significant-bit of the plurality of bits of the digital input signal to be converted to an analog output signal;
the charge-sharing digital-to-analog converter comprises a first plurality of capacitors; and
the first plurality of capacitors are charged by the input voltage and reference voltages during a sampling phase of the digital input signal, wherein charges of the first plurality of capacitors are shared during successive approximations of a first one or more bits of the digital input signal received by the hybrid digital-to-analog converter to provide the analog output signal.

4. The analog-to-digital converter of claim 3 , wherein:
the charge redistribution digital-to-analog converter is configured to convert the first least-significant-bit of the plurality of bits of the digital input signal to be converted to the analog output signal;
the charge redistribution digital-to-analog converter comprises a second plurality of capacitors;
the second plurality of capacitors are charged based on a common mode voltage during the sampling phase of the digital input signal; and
the charge redistribution digital-to-analog converter is configured to perform charge redistribution by connecting the second plurality of capacitors to receive the reference voltages during successive approximations of a second one or more bits of the digital input signal.

5. The analog-to-digital converter of claim 4 , wherein:
the delta sigma digital-to-analog converter is configured to convert the second least-significant-bit of the plurality of bits to be converted to the analog output signal;
the delta sigma digital-to-analog converter comprises a third plurality of capacitors;
the third plurality of capacitors are charged based on the common mode voltage during the sampling phase of the digital input signal; and
the delta sigma digital-to-analog converter is configured to perform charge redistribution by connecting the third plurality of capacitors to receive the reference voltages during successive approximations of a third one or more bits of the digital signal.

6. The analog-to-digital converter of claim 1 , wherein:
the charge-sharing digital-to-analog converter is configured to convert a plurality of most-significant-bits of the plurality of bits, wherein the plurality of most-significant-bits include the first most-significant-bit; and
the charge redistribution digital-to-analog converter is configured to convert a plurality of least-significant-bits of the plurality of bits, wherein the plurality of least-significant-bits include the first least-significant-bit.

7. The analog-to-digital converter of claim 1 , wherein:
the delta sigma digital-to-analog converter is configured to convert one or more least-significant-bits of the plurality of bits; and
the one or more least-significant-bits include the first least-significant-bit.

8. The analog-to-digital converter of claim 1 , wherein the delta sigma digital-to-analog converter is configured to convert the first least significant bit, where the first least significant bit has a lowest corresponding order of magnitude of the plurality of bits.

9. A method comprising:
sampling an analog input signal to generate a plurality of bits;
generating a first digital signal based on the analog input signal via a first analog-to-digital converter, wherein generation of the first digital signal comprises
converting a first most-significant-bit of the plurality of bits via a charge-sharing digital-to-analog converter, and
converting a first least significant bit of the plurality of bits via a charge redistribution digital-to-analog converter,
wherein the first digital signal is generated based on an output of the charge-sharing digital-to-analog converter and an output of the charge redistribution digital-to-analog converter;

generating a second digital signal based on an output of the first analog-to-digital converter via a second analog-to-digital converter including converting a second least significant bit of the plurality of bits via a delta sigma digital-to-analog converter, wherein the second digital signal is generated based on an output of the delta sigma digital-to-analog converter, and wherein the second analog-to-digital converter is a fine conversion analog-to-digital converter relative to the first analog-to-digital converter; and
combining the first digital signal and the second digital signal to provide a resultant output signal.

10. The method of claim 9 , further comprising:
performing successive approximations via the first analog-to-digital converter and based on the plurality of bits to generate the first digital signal; and
suppress noise of the first analog-to-digital converter and output the second digital signal via a decimation filter.

11. The method of claim 9 , further comprising:
receiving a digital input signal having an input voltage via the charge-sharing digital-to-analog converter;
converting, via the charge-sharing digital-to-analog converter, the first most-significant-bit of the plurality of bits of the digital input signal to be converted to an analog output signal;
charging a first plurality of capacitors of the charge-sharing digital-to-analog converter by the input voltage and reference voltages during a sampling phase of the digital input signal; and
sharing charges of the first plurality of capacitors during successive approximations of a first one or more bits of the digital input signal received by the hybrid digital-to-analog converter to provide the analog

Assignees

• Marvell World Trade Ltd

Inventors

• Venca Alessandro
• Nani Claudio
• Ghittori Nicola
• Bosi Alessandro

Classifications

• H03M1/08 Primary

  of noise {(H03M1/0617 takes precedence)} · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M3/322

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M3/378) · CPC title