Laminated structure

Patent metadata

Field	Value
Publication number	US-11219128-B2
Application number	US-202016983202-A
Country	US
Kind code	B2
Filing date	Aug 3, 2020
Priority date	Aug 8, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A laminated structure includes an interconnect structure including first and second product areas and a first interconnect layer, and a first insulating layer formed on the interconnect structure. The first product area includes an opening penetrating the first insulating layer, and the second product area includes an annular groove penetrating the first insulating layer. The laminated structure further includes an electronic component mounted inside the opening in the first product area with an annular gap formed between the electronic component and a wall surface defining the opening, an insulating member located inside the groove in the second product area, a second insulating layer that fills the annular gap and the groove, and covers the first insulating layer, the electronic component, and the insulating member, and a second interconnect layer formed on the second insulating layer, and electrically connected to the first interconnect layer.

First claim

What is claimed is:

1. A laminated structure comprising:
a first product area including a first part of the laminated structure in a thickness direction of the laminated structure;
a second product area adjacent to the first product area, the second product area including a second part of the laminated structure in the thickness direction of the laminated structure;
a first insulating layer included in the first product area and the second product area;
a second insulating layer formed on the upper surface of the first insulating layer;
an opening defined by a first wall surface of the second insulating layer, included in the first product area, penetrating the second insulating layer along a thickness direction of the second insulating layer, and exposing a center portion of the first conductor layer, wherein an outer edge of the first conductor layer is covered by the second insulating layer;
an annular groove defined by mutually opposing outer second wall surface and inner third wall surface of the second insulating layer, included in the second product area, penetrating the second insulating layer along the thickness direction of the second insulating layer, and exposing a portion of the second conductor layer between the second wall surface and the third wall surface of the second insulating layer;
an electronic component mounted on the first conductor layer inside the opening at a center portion of the opening in the first product area with an annular gap between a side surface of the electronic component and the first wall surface opposing the side surface of the electronic component, wherein the annular gap exposes first conductor layer;
an insulating member located on the second conductor layer inside the annular groove at a center portion of the second conductor layer in the second product area, wherein the third wall surface of the second insulating layer forms a side surface of the insulating member;
a third insulating layer that fills the annular gap and the annular groove, and covers the second insulating layer, the electronic component, and the insulating member;
a third interconnect layer formed on an upper surface of the third insulating layer in the first product area, and electrically connected to each of the first interconnect layer and the electronic component; and
a fourth interconnect layer formed on the upper surface of the third insulating layer in the second product area, and electrically connected to the second interconnect layer,
wherein the insulating member and the second insulating layer are made of the same material,
wherein a planar shape of the first conductor layer is larger than a planar shape of the opening,
wherein an annular portion of the second insulating layer is next to the annular groove and on the second conductor layer, and
wherein the insulating member and the annular portion of the second insulating layer have the same height.

2. The laminated structure as claimed in claim 1 , wherein
a planar shape of the second wall surface matches a planar shape of the first wall surface.

3. The laminated structure as claimed in claim 2 , wherein the opening has a planar shape that is rectangular.

4. The laminated structure as claimed in claim 1 , wherein the opening has a planar shape that is rectangular.

5. The laminated structure as claimed in claim 1 , wherein
the electronic component is mounted on the first conductor layer via an adhesive layer in the first product area, and
the insulating member is provided directly on the second conductor layer in the second product area.

6. The laminated structure as claimed in claim 5 , wherein the insulating member has a volume that is approximately the same as a volume of a structure formed by the electronic component and the adhesive layer that are laminated.

7. The laminated structure as claimed in claim 6 , wherein the insulating member has a planar shape that is approximately the same as a planar shape of the electronic component.

8. The laminated structure as claimed in claim 5 , wherein the fourth interconnect layer includes a conductor layer in contact with the insulating member.

9. The laminated structure as claimed in claim 1 , wherein the second insulating layer includes
a fourth insulating layer formed on the upper surface of the first insulating layer, and
a fifth insulating layer formed on an upper surface of the fourth insulating layer.

10. The laminated structure as claimed in claim 1 , wherein a planar shape of the second conductor layer is larger than a combined planar shape of the annular groove and the annular portion.

Assignees

• Shinko Electric Ind Co

Inventors

• Tanaka Izumi

Classifications

• H05K1/186 Primary

  manufactured by mounting on or connecting to patterned circuits before or during embedding · CPC title

• H05K1/182

  associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] · CPC title

• H05K1/16

  incorporating printed electric components, e.g. printed resistors, capacitors or inductors · CPC title

• H05K2201/09609

  Via grid, i.e. two-dimensional array of vias or holes in a single plane · CPC title

• H05K3/0097

  Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards (H05K3/0052 takes precedence) · CPC title