Heterojunction bipolar transistor with marker layer

Patent metadata

Field	Value
Publication number	US-11217685-B2
Application number	US-202016909376-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Sep 23, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

First claim

What is claimed:

1. A structure comprising:
a collector region;
an intrinsic base region above the collector region;
an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material;
an extrinsic base region in electrical contact with the intrinsic base region; and
a spacer on sidewalls of the intrinsic base region including the extrinsic base region, remote from the emitter region.

2. The structure of claim 1 , wherein the marker layer has an etch selectivity to both the emitter material and semiconductor material directly underneath the marker layer.

3. The structure of claim 2 , wherein the marker layer is SiGe material.

4. The structure of claim 2 , further comprising an intrinsic emitter material between the marker layer and the emitter material.

5. The structure of claim 2 , wherein the marker layer is between spacers on sides of the emitter region.

6. The structure of claim 2 , wherein the extrinsic base region is a raised base region composed of epitaxially grown material.

7. The structure of claim 2 , wherein the marker layer is single crystal or polycrystalline material.

8. The structure of claim 2 , wherein the marker layer is discontinuous about the emitter region.

9. The structure of claim 8 , wherein the marker layer is below the extrinsic base material composed of polycrystalline material.

10. The structure of claim 1 , further comprising contacts to the emitter material, the extrinsic base region and in electrical contact to the collector region through a substrate material.

11. The structure of claim 1 , wherein the marker layer has an etch selectivity to the emitter material and the extrinsic base region is a raised base region composed of epitaxial semiconductor material.

12. A structure comprising:
a collector region comprising a first semiconductor material formed over a substrate material acting as a subcollector region;
an intrinsic base region above the collector region and comprising a second semiconductor material different than the first semiconductor material;
an emitter region comprising emitter material, a marker layer and an intrinsic emitter material, the marker layer comprising material different than the second semiconductor material, the emitter material and the intrinsic emitter material; and
a raised extrinsic base region in electrical contact with the intrinsic base region.

13. The structure of claim 12 , wherein the marker layer is SiGe material which has an etch selectivity to the intrinsic emitter material.

14. The structure of claim 12 , wherein the marker layer is vertically between the emitter material and the intrinsic base material and is laterally bounded by spacer material on sides of the emitter region.

15. The structure of claim 12 , further comprising a spacer on sidewalls of the raised extrinsic base region.

16. The structure of claim 12 , wherein the marker layer is single crystal or polycrystalline material.

17. The structure of claim 12 , wherein the marker layer is discontinuous about the emitter region.

18. The structure of claim 12 , wherein an emitter-base junction of the emitter region and the raised extrinsic base material is self-aligned.

19. The structure of claim 12 , wherein the first semiconductor material is Si material and the second semiconductor material is SiGe material, separated from the marker layer by the intrinsic emitter material.

20. A method comprising:
forming a collector material on a substrate;
forming an intrinsic base material on the collector material;
forming an etching marker layer over the intrinsic base material;
forming an emitter material over the etching marker layer;
patterning an emitter region to include at least the emitter material and the etching marker layer, stopping before getting to the intrinsic base material;
forming sidewalls about the emitter region, including the emitter material and the etching marker layer; and
forming an extrinsic base region in electrical contact with the intrinsic base region.

Assignees

• Globalfoundries Us Inc

Inventors

• Ho Herbert
• Jain Vibhor
• Pekarik John J
• Ortolland Claude
• Holt Judson R
• Liu Qizhi
• Ontalus Viorel

Classifications

• H10D62/136

  of heterojunction BJTs  (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861) · CPC title

• H10D10/021

  of heterojunction BJTs [HBT] · CPC title

• H10D10/891

  comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors · CPC title

• H10D10/821

  Vertical heterojunction BJTs · CPC title

• H10D10/80 Primary

  Heterojunction BJTs · CPC title