Heterojunction bipolar transistor fully self-aligned to diffusion region with strongly minimized substrate parasitics and selective pre-structured epitaxial base link

Patent metadata

Field	Value
Publication number	US-10347737-B2
Application number	US-201715619849-A
Country	US
Kind code	B2
Filing date	Jun 12, 2017
Priority date	Jun 16, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Methods for manufacturing a bipolar junction transistor are provided. A method includes providing a semiconductor substrate having a trench isolation, where a pad resulting from a manufacturing of the trench isolation is arranged on the semiconductor substrate, providing an isolation layer on the semiconductor substrate and the pad such that the pad is covered by the isolation layer, removing the isolation layer up to the pad, and selectively removing the pad to obtain an emitter window.

First claim

What is claimed is:

1. A method for manufacturing a bipolar junction transistor, the method comprising:
providing a semiconductor substrate having a trench isolation, wherein a pad resulting from a manufacturing of the trench isolation is arranged on a surface of the semiconductor substrate;
providing an isolation layer on the surface of the semiconductor substrate and the pad such that the pad is covered by the isolation layer;
removing the isolation layer up to the pad such that a surface of the pad is exposed; and
selectively removing the pad to obtain an emitter window.

2. The method according to claim 1 , further comprising:
providing a base layer in the emitter window on the semiconductor substrate.

3. The method according to claim 2 , further comprising:
providing an emitter layer in the emitter window on the base layer.

4. The method according to claim 2 , wherein the isolation layer is a first isolation layer, and the method further comprises:
providing lateral spacers on sidewalls of the emitter window; and
providing a second isolation layer on the first isolation layer and the base layer, such that the base layer and the lateral spacers are covered with the second isolation layer.

5. The method according to claim 4 , further comprising:
providing further lateral spacers within the emitter window on sidewalls of the emitter window that are covered by the second isolation layer.

6. The method according to claim 5 , further comprising:
selectively removing the second isolation layer such that the base layer is partially exposed while maintaining L-shaped parts of the second isolation layer that are covered by the further lateral spacers.

7. The method according to claim 6 , further comprising:
selectively removing the further lateral spacers, such that the L-shaped parts of the second isolation layer that were covered by the further lateral spacers are exposed within the emitter window.

8. The method according to claim 7 , further comprising:
providing an emitter layer on the first isolation layer and in the emitter window such that the emitter layer covers an exposed part of the base layer and the L-shaped parts of the second isolation layer.

9. The method according to claim 8 , further comprising:
providing a sacrificial layer on the emitter layer, the sacrificial layer comprising a recess formed due to the emitter window.

10. The method according to claim 6 , further comprising:
providing an emitter layer on the first isolation layer and in the emitter window such that the emitter layer covers the base layer.

11. The method according to claim 10 , further comprising:
providing a sacrificial layer on the emitter layer thereby overfilling a recess formed by the emitter layer due to the emitter window.

12. The method according to claim 11 , further comprising:
selectively removing the sacrificial layer up to the emitter layer while maintaining a part of the sacrificial layer filling the recess of the emitter layer.

13. The method according to claim 12 , further comprising:
selectively removing the emitter layer up to the isolation layer while maintaining the filled recess of the emitter layer.

14. The method according to claim 1 , further comprising:
providing lateral spacers on sidewalls of the emitter window.

15. The method according to claim 1 , further comprising:
providing a seed layer on the semiconductor substrate and the pad such that the pad is covered by the seed layer,
wherein providing the isolation layer comprises providing the isolation layer on the seed layer, and
wherein removing the isolation layer comprises removing the isolation layer and the seed layer up to the pad such that the surface of the pad is exposed.

16. The method according to claim 15 , further comprising:
selectively removing the seed layer, which is exposed after selectively removing the pad, from sidewalls of the emitter window.

17. The method according to claim 16 , further comprising:
providing lateral spacers on sidewalls of the emitter window,
wherein the lateral spacers are provided on sidewalls of the emitter window such that the lateral spacers laterally cover the seed layer that ends in the emitter window.

18. The method according to claim 17 , wherein providing the semiconductor substrate comprises providing the semiconductor substrate having an oxide layer arranged on the surface of the semiconductor substrate at least between the trench isolation, and wherein the pad is arranged on the oxide layer, the method further comprising:
providing a base layer in the emitter window on the semiconductor substrate;
removing layers arranged on the seed layer, such that the seed layer and the lateral spacers are exposed, while maintaining the lateral spacers and the layers between them; and
selectively removing the lateral spacers, such that the base layer is laterally exposed and cavities are formed between the seed layer and the base layer in which the oxide layer is partially exposed.

19. The method according to claim 18 , further comprising:
providing a base contact layer on the seed layer and an exposed part of the oxide layer.

20. The method according to claim 1 , further comprising:
providing the semiconductor substrate comprises providing the semiconductor substrate having an oxide layer arranged on the surface of the semiconductor substrate at least between the trench isolation, and wherein the pad is arranged on the oxide layer.

21. The method according to claim 20 , further comprising:
removing the oxide layer in the emitter window such that the semiconductor substrate is exposed in the emitter window.

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Dahl Claus
• Tschumakow Dmitri Alex

Classifications

• H01L29/66242 Primary

  Electricity · mapped topic

• H01L29/6634

  Electricity · mapped topic

• H01L29/41708

  Electricity · mapped topic

• H01L29/7322

  Electricity · mapped topic

• H01L29/0817

  Electricity · mapped topic