Quad package with conductive clips connected to terminals at upper surface of semiconductor die

Patent metadata

Field	Value
Publication number	US-11217511-B2
Application number	US-201916379405-A
Country	US
Kind code	B2
Filing date	Apr 9, 2019
Priority date	Apr 9, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A packaged semiconductor device includes a carrier having a die attach surface, a semiconductor die mounted on the die attach surface and comprising first and second conductive terminals disposed on an upper side, a first clip that extends over the semiconductor die and is electrically connected to the first conductive terminal, a second clip that extends over the semiconductor die and is electrically connected to the second conductive terminal, and an electrically insulating encapsulant body that encapsulates the semiconductor die. An outer end of the first clip is exposed from the encapsulant body and provides a point of external electrical contact for the first conductive terminal. An outer end of the second clip is exposed from the same or a different side face of the encapsulant body as the first clip and provides a point of external electrical contact for the second conductive terminal.

First claim

What is claimed is:

1. A packaged semiconductor device, comprising:
a carrier comprising a die attach surface;
a semiconductor die mounted on the die attach surface and comprising first and second conductive terminals disposed on an upper side of the semiconductor die that is opposite from the carrier;
a first clip that extends over the upper side of the semiconductor die and is electrically connected to the first conductive terminal;
a second clip that extends over the upper side of the semiconductor die and is electrically connected to the second conductive terminal;
a plurality of first conductive leads that each extend away from a first side of the carrier; and
an electrically insulating encapsulant body that encapsulates the semiconductor die,
wherein an outer end of the first clip is exposed from a side face of the encapsulant body and provides a point of external electrical contact for the first conductive terminal, and
wherein an outer end of the second clip is exposed from the same or a different side face of the encapsulant body as the outer end of the first clip and provides a point of external electrical contact for the second conductive terminal,
wherein the first clip is oriented transversely relative the first conductive leads,
wherein the first conductive leads are configured as logic leads,
wherein the first conductive leads are electrically connected to the semiconductor die via bond wires.

2. The packaged semiconductor device of claim 1 , wherein the semiconductor die further comprises a plurality of additional conductive terminals disposed on the upper side, wherein the packaged semiconductor device further comprises conductive connectors that electrically connect each of the additional conductive terminals respectively to one of the first leads, and wherein the first clip is oriented transversely relative the conductive connectors.

3. The packaged semiconductor device of claim 1 , wherein the encapsulant body comprises an upper surface that extends over the upper side of the semiconductor die, a lower surface opposite the upper surface, and first and second side faces that extend between the upper and lower surfaces, wherein the first and second side faces form an angled intersection with one another, wherein each of the first leads protrude out of the first side face, and wherein the first clip protrudes out of the second side face.

4. The packaged semiconductor device of claim 3 , wherein the second clip protrudes out of the second side face of the encapsulant body.

5. The packaged semiconductor device of claim 3 , wherein the encapsulant body comprises third and fourth side faces that each extend between the upper and lower surfaces, wherein the first, second, third and fourth side faces collectively form a rectangle, and wherein the second clip protrudes out of the third or fourth side faces of the encapsulant body.

6. The packaged semiconductor device of claim 5 , further comprising:
a plurality of second conductive leads that each extend away from a second side of the carrier in an opposite direction as the first conductive leads,
wherein each of the second conductive leads protrude out of the third side face of the encapsulant body, and
wherein the second clip protrudes out of the fourth side face of the encapsulant body.

7. The packaged semiconductor device of claim 5 , wherein the first clip protrudes out of the second and fourth side faces of the encapsulant body, and wherein the third clip protrudes out of the third side face of the encapsulant body.

8. The packaged semiconductor device of claim 5 , further comprising:
a plurality of third conductive leads that each face and extend away from a third edge side of the carrier,
wherein the third conductive leads extend perpendicularly to the first conductive leads,
wherein each of the third leads protrude out of the fourth side face of the encapsulant body, and
wherein the second clip protrudes out of the third side face of the encapsulant body.

9. The packaged semiconductor device of claim 5 , wherein the semiconductor die further comprises a third conductive terminal disposed on the upper side, wherein the packaged semiconductor device further comprises a third clip that extends over the upper side of the semiconductor die and is electrically connected to the third conductive terminal, and wherein the third clip protrudes out of the fourth side face of the encapsulant body.

10. The packaged semiconductor device of claim 3 , wherein upper surfaces of the first and second clips that face away from the upper surface of the semiconductor die are completely covered by encapsulant material of the encapsulant body.

11. The packaged semiconductor device of claim 3 , wherein upper surfaces of the first and second clips that face away from the upper surface of the semiconductor die are exposed from encapsulant material of the encapsulant body.

12. The packaged semiconductor device of claim 1 , wherein the semiconductor die comprises first and second switching devices integrated therein, wherein each of the first and second switching devices comprise a control terminal, a first output terminal, and a second output terminal, wherein the first conductive terminal is a bond pad connection to the first output terminal of the first switching device, and wherein the second conductive terminal is a bond pad connection to the first output terminal of the second switching device.

13. The packaged semiconductor device of claim 12 , wherein the first output terminal of the first switching device and the first output terminal of the second switching device are each drain terminals, wherein the second output terminal of the first switching device and the second output terminal of the second switching device are each source terminals, and wherein the second output terminal of the first switching device and the second output terminal of the second switching device each directly face and electrically connect with the carrier.

14. A packaged semiconductor device, comprising:
a carrier comprising a die attach surface;
a semiconductor die mounted on the die attach surface;
an electrically insulating encapsulant body that encapsulates the semiconductor die; and
first and second clips that extend over an upper side of the semiconductor die that is opposite from the carrier and protrude out of side faces of the encapsulant body,
a plurality of first conductive leads that each extend away from a first side of the carrier,
wherein the semiconductor die comprises first and second switching devices integrated therein,
wherein each of the first and second switching devices comprise a control terminal, a first output terminal, and a second output terminal,
wherein the first clip is electrically connected to the first output terminal of the first switching device via a bond pad connection at the upper surface, and
wherein the second clip is electrically connected to the first output terminal of the second switching device via a bond pad connection at the upper surface,
wherein the first clip is oriented transversely relative the first conductive leads,
wherein the first conductive leads are configured as logic leads, and
wherein the first conductive leads are electrically connected to the semiconductor die via bond wires.

15. The packaged semiconductor device of claim 14 , further comprising:
electrical connectors connecting the first conductive leads to additional terminals disposed on the upper surface of the semiconductor die,
wherein the first conductive leads protrude out of a different side face of the encapsulant body as the first an

Assignees

• Infineon Technologies Ag

Inventors

• Tey Sock Chien
• Cha Chan Lam
• Chong Hoe Jian
• Danny Koh Cher Hau
• Tan Kim Guan
• Wang mei yong

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/886

  Die-attach connectors and strap connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title