Semiconductor package with semiconductor die directly attached to lead frame and method

Patent metadata

Field	Value
Publication number	US-9711484-B2
Application number	US-201514725156-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	Nov 13, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor die having a major surface and including a conductive pad disposed adjacent and overlapping the major surface, the conductive pad having a first bonding surface spaced apart from the major surface and a sidewall bonding surface extending from the first bonding surface toward the major surface;
a lead including a first region adjacent the semiconductor die and a second region laterally extending away from the first region, wherein the first region has a lead sidewall surface laterally spaced inward from the sidewall bonding surface of the conductive pad, and wherein the first region of the lead faces and overlaps the first bonding surface of the conductive pad;
a conductive layer affixed to the first bonding surface of the conductive pad, affixed to the sidewall bonding surface of the conductive pad, affixed to the first region, and affixed to the lead sidewall surface thereby electrically connecting the conductive pad to the lead, wherein a first portion of the conductive layer is interposed between the first bonding surface of the conductive pad and the first region of the lead; and
an encapsulant covering the semiconductor die and at least portions of the lead,
wherein:
the first region of the lead is thinner than the second region of the lead;
the first region includes a first region first surface and a first region second surface opposite to the first region first surface;
the lead sidewall surface extends between the first region first surface and the first region second surface;
the second region includes a second region first surface contiguous with the first region first surface and a second region second surface opposite to the second region first surface;
the conductive layer comprises a continuous conductive layer affixed to the first region first surface, the lead sidewall surface, the first region second surface, and the second region second surface;
the continuous conductive layer affixed to the first region second surface is covered by the encapsulant; and
the continuous conductive layer affixed to the second region second surface is exposed to the outside of the encapsulant.

2. The semiconductor package of claim 1 , wherein the first region further comprises a protrusion protruding towards the conductive pad.

3. The semiconductor package of claim 2 , wherein the conductive layer covers the protrusion.

4. The semiconductor package of claim 1 , wherein:
the lead includes a through-hole in the first region corresponding to the conductive pad, the through-hole passing through the first region between a first surface and a second surface opposite to the first surface, and the through-hole is filled with the conductive layer.

5. The semiconductor package of claim 1 , wherein:
the conductive pad further includes a stud bump disposed adjacent the first bonding surface and protruding towards the lead, and wherein the conductive layer is affixed to all exposed surfaces of the stud bump.

6. The semiconductor package of claim 5 , wherein:
the conductive layer has a non-uniform thickness between the stud bump and the first region of the lead.

7. The semiconductor package of claim 1 , further comprising:
a die pad shaped of a rectangular plate,
wherein:
the conductive layer comprises one of an electroplated layer or an electroless plated layer;
the first region of the lead is thinner than the second region of the lead;
the first region includes a first region first surface and a first region second surface opposite to the first region first surface;
the lead sidewall surface extends between the first region first surface and the first region second surface;
the second region includes a second region first surface contiguous with the first region first surface and a second region second surface opposite to the second region first surface; and
the conductive layer comprises a continuous conductive layer affixed to the first region first surface, the lead sidewall surface, the first region second surface, and the second region second surface.

8. The semiconductor package of claim 1 , wherein:
the lead, the conductive pad, and the conductive layer comprise the same metal, and wherein a second portion of the conductive layer is affixed to the second region of the lead, and wherein the first portion is thicker than the second portion.

9. A semiconductor package comprising:
a semiconductor die having a first surface and a second surface opposite to the first surface and including a first conductive pad disposed adjacent to and overlapping the first surface, the first conductive pad having a first bonding surface spaced apart from the first surface and a sidewall bonding surface extending from the first bonding surface toward the first surface;
a lead comprising a first region adjacent the first surface of the semiconductor die and a second region laterally extending away from the first region, wherein the first region has a lead sidewall surface laterally spaced inward from the sidewall bonding surface of the first conductive pad, and wherein the first region overlaps the first bonding surface of the first conductive pad, and wherein the first region is thinner than the second region;
an electrochemically deposited conductive layer affixed to the first bonding surface of the first conductive pad, affixed to the sidewall bonding surface of the first conductive pad, affixed to the first region, affixed to at least a portion of the second region, and affixed to the lead sidewall surface thereby electrically connecting the first conductive pad to the lead, wherein a first portion of the electrochemically deposited conductive layer is interposed between the first bonding surface of the first conductive pad and the first region of the lead; and
an encapsulant encapsulating the semiconductor die,
wherein:
the first region of the lead includes a first region first surface and a first region second surface opposite to the first region first surface;
the lead sidewall surface extends between the first region first surface and the first region second surface;
the second region of the lead includes a second region first surface contiguous with the first region first surface and a second region second surface opposite to the second region first surface;
the electrochemically deposited conductive layer comprises a continuous conductive layer affixed to the first region first surface, the lead sidewall surface, the first region second surface, and the second region second surface;
the continuous conductive layer affixed to the first region second surface is covered by the encapsulant; and
the continuous conductive layer affixed to the second region second surface is exposed to the outside of the encapsulant.

10. The semiconductor package of claim 9 , wherein:
a portion of the electrochemically deposited conductive layer is thicker in the first region than in the second region.

11. The semiconductor package of claim 9 , further comprising:
a die pad, wherein the electrochemically deposited conductive layer is interposed between the first surface of the semiconductor die and the die pad, and wherein the electrochemically deposited conductive layer comprises one of an electroplated layer or an electroless plated layer.

12. The semiconductor package of claim 9 , wherein:
the first conductive pad further includes a conductive bump interposed between the first conductive pad and the lead; and
the electrochemically deposited conductive layer is interposed between the lead and the first conductive pad so as to entirely cover outer surfaces of the conductive bump.

Assignees

• Amkor Technology Inc

Inventors

• Paek Jong Sik
• Park Doo Hyun
• Lee Wang Gu
• Song Yong
• Kang Sung Geun

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title