Phase-locked loop (PLL) calibration

Patent metadata

Field	Value
Publication number	US-11212017-B2
Application number	US-202017016263-A
Country	US
Kind code	B2
Filing date	Sep 9, 2020
Priority date	Sep 13, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

An apparatus is disclosed that implements phase-locked loop (PLL) calibration. In an example aspect, the apparatus includes a PLL and a signal extraction path. The PLL includes an error determiner with an error output node and a loop filter with a filter input node and a filter output node. The filter input node is coupled to the error output node. The PLL also includes a voltage-controlled oscillator (VCO) with a VCO input node. The VCO input node is coupled to the filter output node. The PLL further includes a PLL tap node coupled between the filter output node and the VCO input node. The signal extraction path includes at least one switch, with the signal extraction path coupled to the PLL tap node.

First claim

What is claimed is:

1. An apparatus comprising:
a phase-locked loop (PLL) comprising:
an error determiner comprising an error output node;
a loop filter comprising a filter input node and a filter output node, the filter input node coupled to the error output node;
a voltage-controlled oscillator (VCO) comprising a VCO input node, the VCO input node coupled to the filter output node; and
a PLL tap node coupled between the filter output node and the VCO input node; and

a signal extraction path comprising at least one switch and a voltage-to-current converter (V2I converter), the at least one switch coupled between the PLL tap node and the V2I converter.

2. The apparatus of claim 1 , further comprising:
an analog-to-digital converter (ADC) comprising an ADC input node, wherein:
the at least one switch comprises a first terminal and a second terminal; and
the first terminal is coupled to the PLL tap node, and the second terminal is coupled to the ADC input node, such that the at least one switch is coupled between the PLL tap node and the ADC input node.

3. The apparatus of claim 2 , wherein the at least one switch, responsive to being in a closed state, is configured to route a signal from the filter output node toward the ADC input node.

4. The apparatus of claim 2 , wherein:
the V2I converter comprises a V2I-converter input node and a V2I-converter output node; and
the V2I-converter input node is coupled to the PLL tap node, and the V2I-converter output node is coupled to the ADC input node, such that the V2I converter is coupled in series with the at least one switch between the PLL tap node and the ADC input node.

5. The apparatus of claim 2 , further comprising:
a receive chain,
wherein the receive chain comprises the ADC.

6. The apparatus of claim 5 , further comprising:
at least one antenna,
wherein the receive chain comprises a receiver switch coupled between the at least one antenna and the ADC input node, the receiver switch configured to enable wireless signal reception via the at least one antenna and using the ADC responsive to the receiver switch being in a closed state.

7. The apparatus of claim 6 , further comprising:
a display screen; and
at least one processor operably coupled to the display screen and the ADC of the receive chain, the at least one processor configured to present one or more graphical images on the display screen based on one or more wireless signals received via the at least one antenna and using the ADC and the PLL.

8. The apparatus of claim 1 , wherein:
the signal extraction path is configured to extract an extracted signal from the PLL tap node responsive to the at least one switch being in a closed state.

9. The apparatus of claim 8 , wherein:
the error determiner is configured to provide a determined error signal at the error output node;
the loop filter is configured to produce a filtered error signal at the filter output node based on the determined error signal; and
the signal extraction path is configured to:
extract the filtered error signal from the PLL as the extracted signal via the PLL tap node; and
route the extracted signal to the at least one switch.

10. The apparatus of claim 9 , wherein:
the error determiner comprises a feedback input node and a reference input node, the reference input node configured to accept a reference signal;
the VCO comprises a VCO output node; and
the PLL comprises:
a frequency divider coupled between the VCO output node and the feedback input node.

11. The apparatus of claim 1 , wherein:
the PLL comprises at least one calibration parameter input node; and
the apparatus further comprises a feedback path coupled between the signal extraction path and the at least one calibration parameter input node.

12. The apparatus of claim 11 , wherein:
the PLL comprises a PLL feedback loop and PLL control circuitry;
the PLL feedback loop comprises the error determiner, the loop filter, the VCO, and the PLL tap node;
the PLL control circuitry comprises the at least one calibration parameter input node and a current offset circuit; and
the current offset circuit is coupled between the at least one calibration parameter input node and the PLL feedback loop.

13. The apparatus of claim 12 , wherein:
the feedback path comprises digital circuitry configured to calibrate the PLL based on an extracted signal that is extracted from the PLL feedback loop via the at least one switch of the signal extraction path;
the current offset circuit is configured to apply a current signal to the PLL feedback loop; and
the digital circuitry is configured to adjust a current magnitude of the current signal applied by the current offset circuit based on the extracted signal.

14. The apparatus of claim 13 , wherein:
the digital circuitry is configured to adjust the current magnitude of the current signal applied by the current offset circuit responsive to a magnitude of a spur corresponding to at least one frequency component of the extracted signal.

15. The apparatus of claim 12 , wherein:
the error determiner comprises a feedback input node;
the error determiner comprises a phase-frequency detector and a charge pump coupled together in series between the feedback input node and the error output node; and
the current offset circuit is coupled between the at least one calibration parameter input node and the filter input node.

16. The apparatus of claim 11 , wherein:
the VCO comprises a VCO modulation input node;
the PLL comprises a PLL feedback loop and PLL control circuitry;
the PLL feedback loop comprises the error determiner, the loop filter, the VCO, and the PLL tap node;
the PLL control circuitry comprises the at least one calibration parameter input node, a multiplier, and a modulation switch; and
the multiplier comprises a gain control node, a modulation input node, and a multiplier output node; the gain control node coupled to the at least one calibration parameter input node, the multiplier output node coupled to the VCO modulation input node, and the modulation input node coupled to the modulation switch.

17. The apparatus of claim 16 , wherein:
the modulation switch comprises a pole, a first throw, and a second throw; the pole coupled to the modulation input node, the first throw configured to accept a first frequency-modulation signal for a regular operational mode, the second throw configured to accept a second frequency-modulation signal for a calibration operational mode.

18. The apparatus of claim 17 , wherein:
the modulation switch comprises a third throw, the third throw configured to accept a third frequency-modulation signal for another calibration operational mode.

19. The apparatus of claim 16 , wherein:
the feedback path comprises digital circuitry configured to calibrate the PLL based on an extracted signal that is extracted from the PLL feedback loop via the at least one switch of the signal extraction path;
the multiplier is configured to apply a gain to a frequency-modulation signal that is routed to the VCO modulation input node to modulate an output signal of the PLL; and
the digital circuitry is configured to adjust an amount of the gain applied to the frequency-modulation signal by the multiplier based on the extracted signal.

20. The apparatus of claim 19 , wherein:
the digital circuitry is configured to adjust the amount of the gain applied to the frequency-modulation signal responsive to a magnitude of at least one frequency component of the extracted

Assignees

• Qualcomm Inc

Inventors

• Jones Philip
• Mylonas Georgios
• Summers Andrew Gordon
• Popov Oleg

Classifications

• H04B17/22 Primary

  for calibration of the receiver components · CPC title

• H03C3/0958

  applying frequency modulation by varying the characteristics of the voltage controlled oscillator · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title