Fast frequency hopping phase locked loop

Patent metadata

Field	Value
Publication number	US-10063366-B2
Application number	US-201615269320-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Apr 25, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

First claim

What is claimed is:

1. A method for wireless communication comprising:
changing a frequency allocation at a transceiver;
applying a tuning voltage to a first input port of a voltage controlled oscillator (VCO) of a phase locked loop; and
hopping a local oscillator frequency to a new center frequency based at least in part on the changed frequency allocation, the hopping to the new center frequency based at least in part on a frequency adjustment in baseband including applying a first frequency adjustment signal to a second input port of the VCO.

2. The method of claim 1 , further comprising calibrating a two-point modulation of the phase locked loop.

3. The method of claim 2 , in which the calibrating comprises a gain calibration.

4. The method of claim 2 , in which the calibrating comprises a delay calibration.

5. The method of claim 1 further comprising cancelling at least a portion of noise generated by a delta-sigma modulator.

6. The method of claim 2 , in which the two-point modulation comprises modulating the phase locked loop through a high pass path.

7. The method of claim 6 , in which the two-point modulation further comprises modulating the phase locked loop through a low pass path.

8. The method of claim 1 , further comprising receiving a resource allocation message from a base station, the resource allocation message comprising frequency allocation information.

9. The method of claim 1 , further comprising up-converting a signal using the new center frequency.

10. An apparatus for wireless communication comprising:
a local oscillator;
a phase detector coupled to the local oscillator, the local oscillator operable to receive a reference frequency for a transceiver;
a voltage controlled oscillator (VCO) coupled to the phase detector, the VCO including a first input port and a second input port to respectively receive a tuning voltage and a first frequency adjustment signal;
a frequency divider coupled to the VCO and to the phase detector to complete a feedback loop of a phase locked loop; and
a control unit coupled to the local oscillator, the control unit operable to determine a change in frequency allocation at the transceiver, the control unit operable to cause the local oscillator to hop from the reference frequency to a new center frequency based at least in part on the changed frequency allocation, the hopping to the new center frequency based at least in part on a frequency adjustment in baseband where the first frequency adjustment signal is applied to the second input port of the VCO.

11. The apparatus of claim 10 , further comprising a calibration circuit operable to calibrate a two-point modulation of the phase locked loop.

12. The apparatus of claim 11 , in which the calibration circuit further comprises a gain calibration circuit.

13. The apparatus of claim 11 , in which the calibration circuit further comprises a delay calibration circuit.

14. The apparatus of claim 10 , further comprising a filter to cancel at least a portion of noise generated by a delta-sigma modulator.

15. The apparatus of claim 10 , in which the control unit is coupled to the VCO to cause the first frequency adjustment signal to be provided to the VCO to modulate the phase locked loop through a high pass path.

16. The apparatus of claim 15 , in which the control unit is coupled to the VCO to cause a second frequency adjustment signal to be provided to the frequency divider to modulate the phase locked loop through a low pass path.

17. The apparatus of claim 10 , further comprising a receiver coupled to the control unit to receive a resource allocation message from a base station, the resource allocation message comprising frequency allocation information.

18. The apparatus of claim 10 , in which the phase detector is further configured to up-convert a signal using the new center frequency.

19. An apparatus for wireless communication comprising:
means for generating a phase locked loop reference frequency;
means for detecting a phase difference between a first frequency and a second frequency, the phase difference detecting means coupled to the phase locked loop reference frequency generating means, the phase locked loop reference frequency generation means operable to receive an original reference frequency for a transceiver;
a voltage controlled oscillator (VCO) coupled to the phase difference detecting means, the VCO including a first input port and a second input port to respectively receive a tuning voltage and a first frequency adjustment signal;
a frequency divider coupled to the VCO and to the phase difference detecting means to complete a feedback loop of a phase locked loop; and
control means for determining a frequency change allocation at the transceiver, coupled to the phase locked loop reference frequency generation means, the control means comprising means for causing the reference frequency generation means to hop from the original reference frequency to a new center frequency based at least in part on the changed frequency allocation, the hopping to the new center frequency based at least in part on a frequency adjustment in baseband where the first frequency adjustment signal is applied to the second input port of the VCO.

20. The apparatus of claim 19 , further comprising means for calibrating a two-point modulation of the phase locked loop.

21. The apparatus of claim 20 , in which the calibration means further comprises gain calibration means.

22. The apparatus of claim 20 , in which the calibration means further comprises delay calibration means.

23. The apparatus of claim 19 , further comprising means for cancelling at least a portion of noise generated by a delta-sigma modulator.

24. The apparatus of claim 19 , further comprising a receiver coupled to the control means to receive a resource allocation message from a base station, the resource allocation message comprising frequency allocation information.

Assignees

• Qualcomm Inc

Inventors

• Zanuso Marco
• MARUCCI Giovanni
• Hung Tsai-Pi
• Gatta Francesco
• Sun Bo

Classifications

• H03L7/08

  Details of the phase-locked loop · CPC title

• H04W72/0453

  Resources in frequency domain, e.g. a carrier in FDMA · CPC title

• H04B2201/71353

  Fast frequency hopping · CPC title

• H04B1/713 Primary

  using frequency hopping · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title