Package structure and method of fabrcating the same

US11211341B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11211341-B2
Application numberUS-201916719984-A
CountryUS
Kind codeB2
Filing dateDec 19, 2019
Priority dateDec 19, 2019
Publication dateDec 28, 2021
Grant dateDec 28, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulate the die and the plurality of through vias. The plurality of first connectors are electrically connected to the plurality of through vias. The warpage control material is disposed over a first surface of the die. The protection material is disposed over the encapsulant, around the plurality of first connectors and the warpage control material.

First claim

Opening claim text (preview).

What is claimed is: 1. A package structure, comprising: a die; a plurality of through vias, disposed around the die; an encapsulant, laterally encapsulating the die and the plurality of through vias; a plurality of first connectors, electrically connected to the plurality of through vias; a warpage control material, disposed over the die; and a protection material, disposed over the encapsulant, around the plurality of first connectors and the warpage control material, wherein a coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant. 2. The package structure of claim 1 , wherein the warpage control material is disposed to cover an entire surface of the die. 3. The package structure of claim 1 , wherein the warpage control material is disposed to partially cover surfaces of the die and the encapsulant. 4. The package structure of claim 1 , further comprising a dielectric layer disposed between the die and the warpage control material, and between the encapsulant and the protection material, wherein the plurality of first connectors extend through the dielectric layer to be in contact with the plurality of through vias. 5. The package structure of claim 1 , wherein the warpage control material comprises a base material and a plurality of fillers in the base material. 6. The package structure of claim 1 , wherein a Young's modulus of the warpage control material is greater than a Young's modulus of the encapsulant, and the Young's modulus of the encapsulant is greater than a Young's modulus of the protection material. 7. The package structure of claim 1 , wherein the coefficient of thermal expansion of the encapsulant is less than a coefficient of thermal expansion of the warpage control material. 8. A package structure, comprising: a die; a plurality of through vias, disposed around the die; an encapsulant, laterally encapsulating the die and the plurality of through vias; a plurality of first connectors, electrically connected to the plurality of through vias; a warpage control material, disposed over a first surface of the die; and a protection material, disposed over a first surface of the encapsulant and a top surface of the warpage control material, around the plurality of first connectors and the warpage control material, wherein a coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant. 9. The package structure of claim 8 , further comprising an adhesive disposed between the die and the warpage control material. 10. The package structure of claim 8 , further comprising a dielectric layer disposed between the die and the warpage control material, and between the encapsulant and the protection material, wherein the plurality of first connectors extend through the dielectric layer to be in contact with the plurality of through vias. 11. The package structure of claim 8 , further comprising: a first redistribution structure disposed between the die and the warpage control material, and between the encapsulant and the protection material, wherein the plurality of first connectors and the plurality of through vias are in contact with a metallization pattern of the first redistribution structure; a second redistribution structure disposed on a second surface of the die and a second surface of the encapsulant to electrically connect to the plurality of through vias; and a plurality of second connectors to electrically connect to the second redistribution structure. 12. The package structure of claim 8 , wherein the warpage control material comprises a base material and a plurality of fillers in the base material. 13. The package structure of claim 8 , wherein a Young's modulus of the warpage control material is greater than a Young's modulus of the protection material. 14. The package structure of claim 8 , wherein the coefficient of thermal expansion of the encapsulant is less than a coefficient of thermal expansion of the warpage control material. 15. A method of manufacturing a package structure, comprising: forming a plurality of through vias around a die; forming an encapsulant to laterally encapsulate the die and the plurality of through vias; forming a plurality of connectors to electrically connect to the plurality of through vias; forming a warpage control material over a first surface of the die; and forming a protection material over a first surface of the encapsulant, around the plurality of first connectors and the warpage control material, wherein a coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant. 16. The method of claim 15 , wherein the protection material is further formed over a top surface of the warpage control material. 17. The method of claim 15 , wherein the warpage control material comprises a base material and a plurality of fillers in the base material. 18. The method of claim 15 , wherein a Young's modulus of the warpage control material is greater than a Young's modulus of the protection material. 19. The method of claim 15 , wherein the forming the plurality of first connectors comprises performing a reflow process after the forming the warpage control material. 20. The method of claim 15 , further comprising: performing a curing process after forming the protection material; and forming openings in the protection material to expose the plurality of connectors.

Assignees

Inventors

Classifications

  • On different surfaces · CPC title

  • extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

  • Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

  • by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

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What does patent US11211341B2 cover?
Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulate the die and the plurality of through vias. The plurality of first connectors are electrically connected to the plurali…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W74/019. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 28 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).