Semiconductor device

Patent metadata

Field	Value
Publication number	US-11211339-B2
Application number	US-201916703468-A
Country	US
Kind code	B2
Filing date	Dec 4, 2019
Priority date	Oct 19, 2015
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor die, wherein the semiconductor die has an insulative layer and a conductive feature in the insulative layer; and
a shield in contact with a lateral surface of the conductive feature,

wherein the lateral surface of the conductive feature is aligned with an edge of the insulative layer.

2. The semiconductor device of claim 1 , wherein the insulative layer surrounds the semiconductor die.

3. The semiconductor device of claim 1 , wherein a height of the conductive feature is substantially equal to a thickness of the insulative layer.

4. The semiconductor device of claim 1 , further comprising an insulative material isolated from the insulative layer by the conductive feature, and the insulative material includes a lateral surface aligned with the lateral surface of the conductive feature and the edge of the insulative layer.

5. The semiconductor device of claim 4 , wherein the conductive feature has a substantially semi-circular cross-sectional shape or a substantially U cross-sectional shape.

6. The semiconductor device of claim 1 , wherein the conductive feature further includes one or more extension portions extended toward a direction opposite to the edge of the insulative layer.

7. The semiconductor device of claim 1 , further comprising a ground terminal over a bottom surface of the insulative layer, wherein the shield is electrically connected to the ground terminal through the conductive feature.

8. The semiconductor device of claim 1 , further comprising an active redistribution layer (RDL) over the insulative layer and electrically connected to the semiconductor die.

9. The semiconductor device of claim 8 , wherein the conductive feature is electrically disconnected from the active RDL.

10. A semiconductor device, comprising:
a semiconductor die;
a first insulative layer surrounding the semiconductor die; and
a conductive feature extended through the first insulative layer, wherein the conductive feature includes a top surface, a bottom surface and a lateral surface substantially perpendicular to the top surface and the bottom surface,

wherein the lateral surface of the conductive feature is aligned with an edge of the first insulative layer, and the conductive feature is electrically connected to a shield through the lateral surface of the conductive feature.

11. The semiconductor device of claim 10 , wherein a height of the conductive feature is substantially equal to a thickness of the first insulative layer.

12. The semiconductor device of claim 10 , further comprising:
a second insulative layer disposed over the semiconductor die, the conductive feature and the first insulative layer;
an active redistribution layer (RDL) disposed in the second insulative layer and electrically connected to the semiconductor die; and
a dummy RDL disposed in the second insulative layer and electrically connected to the shield and the top surface of the conductive feature, wherein the dummy RDL is disconnected from the semiconductor die;
a terminal electrically connected to the bottom surface of the conductive feature.

13. The semiconductor device of claim 12 , wherein a lateral surface of the dummy RDL is aligned with an edge of the second insulative layer and the lateral surface of the conductive feature, and the lateral surface of the dummy RDL is in contact with the shield.

14. The semiconductor device of claim 12 , wherein the semiconductor die comprises a conductive pillar electrically connecting the semiconductor die and the active RDL.

15. The semiconductor device of claim 12 , further comprising a conductive post in the first insulative layer and electrically connected to the active RDL.

16. A semiconductor device, comprising:
a semiconductor die;
an insulative layer surrounding the semiconductor die, wherein the insulative layer includes an edge; and
a conductive feature proximal to the edge of the insulative layer, wherein the conductive feature includes two lateral surfaces aligned with the edge of the insulative layer.

17. The semiconductor device of claim 16 , further comprising an insulative material isolated from the insulative layer by the conductive feature, wherein the insulative material includes a lateral surface aligned with the lateral surfaces of the conductive feature and the edge of the insulative layer.

18. The semiconductor device of claim 17 , wherein the conductive feature has a substantially semi-circular cross-sectional shape or a substantially U cross-sectional shape.

19. The semiconductor device of claim 17 , further comprising a shield in contact with both of the two lateral surfaces of the conductive feature.

20. The semiconductor device of claim 16 , further comprising:
a conductive structure disposed on a first end of the conductive feature; and
a terminal disposed over a second end of the conductive feature,

wherein the conductive structure comprises a lateral surface aligned with at least one of the two lateral surfaces of the of conductive feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chuei-Tang
• Chen Vincent
• Tang Tzu-Chun
• Yu Chen-Hua
• Yang Ching-Feng
• Liu Ming-Kai
• Wang Yen-Ping
• Wu Kai-Chiang
• Chang Shou Zen
• Lin Wei-Ting
• Lu Chun-Lin

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title