Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10043761-B2
Application number	US-201514886996-A
Country	US
Kind code	B2
Filing date	Oct 19, 2015
Priority date	Oct 19, 2015
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor die;
an insulative layer surrounding the semiconductor die, wherein the insulative layer includes an upper surface and an edge connected to the upper surface;
a post passivation interconnect (PPI) over the insulative layer and the semiconductor die;
a conductive feature in the edge of the insulative layer and extended through the insulative layer, wherein the conductive feature includes an upper surface exposed from the upper surface of the insulative layer, and a lateral surface exposed from the edge of the insulative layer;
an Electromagnetic Interference (EMI) shield substantially covering the edge of the insulative layer and being in contact with the upper surface of the conductive feature exposed from the upper surface of the insulative layer and the lateral surface of the conductive feature exposed from the edge of the insulative layer.

2. The semiconductor device of claim 1 , wherein the conductive feature is extended through the insulative layer along a direction parallel to a thickness of the semiconductor die.

3. The semiconductor device of claim 2 , wherein the conductive feature includes a recessed portion, the recessed portion is recessed from the lateral surface of the conductive feature and toward the semiconductor die.

4. The semiconductor device of claim 3 , wherein the recessed portion includes an inner surface and the inner surface is isolated from the insulative layer.

5. The semiconductor device of claim 3 , wherein the conductive feature further includes an extension portion connected to the recessed portion, and the extension portion is extended further away from the lateral surface than the recessed portion.

6. The semiconductor device of claim 3 , wherein the conductive feature further includes an extension portion connected to the recessed portion, and the extension portion is extended further away from the lateral surface than the recessed portion and includes at least two branches respectively extended in a different radial direction.

7. The semiconductor device of claim 1 , wherein the conductive feature is connected to ground.

8. The semiconductor device of claim 1 , further comprising:
an electronic component over the PPI, wherein the electronic component is electrically connected to the semiconductor die through the PPI.

9. The semiconductor device of claim 1 , wherein the lateral surface of the conductive feature includes a height and a width, an aspect ratio of the height to the width is about 1.0, wherein the height is measured along a direction parallel to a thickness of the semiconductor die.

10. The semiconductor device of claim 1 , further comprising a seal ring over and electrically connected to the conductive feature.

11. The semiconductor device of claim 4 , wherein the conductive feature includes another lateral surface exposed from the edge of the insulative layer.

12. The semiconductor device of claim 11 , wherein the another lateral surface of the conductive feature is in contact with the EMI shield.

13. The semiconductor device of claim 12 , wherein the inner surface is a continuous inner surface between the two lateral surfaces exposed from the edge of the insulative layer.

14. The semiconductor device of claim 13 , wherein the inner surface is curved into the insulative layer.

15. The semiconductor device of claim 11 , further comprising:
an insulative material between the two lateral surfaces exposed from the edge of the insulative layer, and not in contact with the insulative layer.

16. The semiconductor device of claim 1 , wherein the conductive feature is electrically disconnected from the PPI.

17. A semiconductor device, comprising:
a semiconductor die;
an insulative layer surrounding the semiconductor die;
an active redistribution layer (RDL) over the insulative layer electrically connected to the semiconductor die;
a dummy RDL over an edge of the insulative layer and electrically disconnected from the semiconductor die;
a conductive feature in the edge of the insulative layer, wherein the conductive feature is in contact with the dummy RDL, and the conductive feature includes a lateral surface exposed from the edge of the insulative layer; and
an Electromagnetic Interference (EMI) shield substantially covering the edge of the insulative layer and being in contact with the lateral surface of the conductive feature exposed from the edge of the insulative layer.

18. The semiconductor device of claim 17 , wherein the conductive feature includes a recessed portion, the recessed portion is recessed from the lateral surface of the conductive feature and toward the semiconductor die.

19. The semiconductor device of claim 18 , wherein the recessed portion includes an inner surface and the inner surface is isolated from the insulative layer.

20. A semiconductor device, comprising:
a semiconductor die;
an insulative layer surrounding the semiconductor die, wherein the insulative layer includes an edge substantially in parallel to a direction of a thickness of the semiconductor die;
a conductive feature in the edge of the insulative layer, wherein the conductive feature includes a lateral surface exposed from the edge of the insulative layer, and a thickness of the conductive feature is substantially equal to or greater than the thickness of the semiconductor die; and
an Electromagnetic Interference (EMI) shield substantially covering the edge of the insulative layer and being in contact with the lateral surface of the conductive feature exposed from the edge of the insulative layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chuei-Tang
• Chen Vincent
• Tang Tzu-Chun
• Yu Chen-Hua
• Yang Ching-Feng
• Liu Ming-Kai
• Wang Yen-Ping
• Wu Kai-Chiang
• Chang Shou Zen
• Lin Wei-Ting
• Lu Chun-Lin

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title