Semiconductor device

Patent metadata

Field	Value
Publication number	US-11211288-B2
Application number	US-201816123214-A
Country	US
Kind code	B2
Filing date	Sep 6, 2018
Priority date	Sep 7, 2017
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.

First claim

What is claimed is:

1. A semiconductor device comprising:
first and second trenches formed in a single dielectric layer, disposed in parallel to each other, and opened in one reference plane;
an etching stop layer on which the first trench, the second trench, and the single dielectric layer are formed such that the etching stop layer covers entire bottom surfaces of the first trench, the second trench, and the single dielectric layer;
a first wiring formed in the first trench;
a second wiring formed in the second trench;
a first impedance adjustment layer formed in an inner surface of the first trench; and
a second impedance adjustment layer formed in an inner surface of the second trench,
wherein a portion of the single dielectric layer is interposed between a side surface of the first trench and a side surface of the second trench, and is configured to insulate the first wiring and the second wiring from each other,
wherein the first and second impedance adjustment layers formed between the first wiring and the second wiring are configured to adjust an impedance between the first wiring and the second wiring, and each of the first and second impedance adjustment layers serves as an inductor, and
wherein a material of the first and second impedance adjustment layers includes a Mott-insulator.

2. The semiconductor device of claim 1 , wherein the material of the first and second impedance adjustment layers includes vanadium dioxide.

3. The semiconductor device of claim 1 , further comprising: a first barrier layer formed between the first impedance adjustment layer and the first wiring; and a second barrier layer formed between the second impedance adjustment layer and the second wiring,
wherein the first and second impedance adjustment layers are in contact with the first and second barrier layers, respectively.

4. A semiconductor device comprising:
a first trench formed in a first dielectric layer;
a second trench formed in a second dielectric layer stacked above the first dielectric layer;
a first wiring formed in the first trench;
a second wiring formed in the second trench;
a third dielectric layer interposed between an upper opening of the first trench and a bottom surface of the second trench, and configured to insulate the first wiring and the second wiring from each other;
an impedance adjustment layer formed between the first wiring and the second wiring, configured to adjust an impedance between the first wiring and the second wiring, and serving as an inductor; and
a cap layer formed on the first wiring,
wherein a material of the impedance adjustment layer includes a Mott-insulator,
the third dielectric layer is formed on the cap layer,
the second wiring is formed on the third dielectric layer, and
the impedance adjustment layer is formed between the cap layer and the third dielectric layer, and is in contact with the cap layer.

5. A semiconductor device comprising:
a first trench formed in a first dielectric layer;
a second trench formed in a second dielectric layer stacked above the first dielectric layer;
a first wiring formed in the first trench;
a second wiring formed in the second trench;
a third dielectric layer interposed between an upper opening of the first trench and a bottom surface of the second trench, and configured to insulate the first wiring and the second wiring from each other;
an impedance adjustment layer formed between the first wiring and the second wiring, configured to adjust an impedance between the first wiring and the second wiring, and serving as an inductor; and an etching stop layer formed above the third dielectric layer,
wherein the third dielectric layer is formed on the first wiring,
the second wiring is formed on the etching stop layer, and
the impedance adjustment layer is formed between the third dielectric layer and the etching stop layer, and is in contact with the etching stop layer.

6. The semiconductor device of claim 4 , wherein the material of the impedance adjustment layer includes vanadium dioxide.

7. The semiconductor device of claim 5 , wherein the material of the impedance adjustment layer includes vanadium dioxide.

Assignees

• Tokyo Electron Ltd

Inventors

• Nakabayashi Hajime
• Akiyama Koji

Classifications

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title