Apparatus and method for centrally controlling common mode voltages for a set of receivers

Patent metadata

Field	Value
Publication number	US-10243531-B1
Application number	US-201715701072-A
Country	US
Kind code	B1
Filing date	Sep 11, 2017
Priority date	Sep 11, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.

First claim

What is claimed is:

1. An apparatus, comprising:
a differential signal processing circuit comprising:
a first load device, a first input transistor, and a first current source transistor coupled in series between a first upper voltage rail and a lower voltage rail, wherein the first input transistor includes a first gate configured to receive a positive component of an input differential signal and a first drain configured to produce a negative component of an output differential signal; and
a second load device, a second input transistor, and a current control source transistor coupled in series between the first upper voltage rail and the lower voltage rail, wherein the second input transistor includes a second gate configured to receive a negative component of the input differential signal and a second drain configured to produce a positive component of the output differential signal;

a local common mode voltage control circuit configured to receive an external common mode control current and generate therefrom a bias voltage for gates of the first and second current source transistors for setting a common mode voltage of the output differential signal to substantially a target common mode voltage; and
an external common mode voltage control circuit configured to generate the external common mode control current.

2. The apparatus of claim 1 , wherein the local common mode voltage control circuit comprises a transistor including a drain configured to receive the external common mode control current and a gate configured to produce the bias voltage.

3. The apparatus of claim 1 , wherein the external common mode voltage comprises:
an input circuit configured to generate a replica input voltage related to a common mode voltage of the input differential signal;
a replica circuit configured to generate a replica common mode voltage based on the replica input voltage;
a target common mode voltage setting circuit configured to generate the target common mode voltage;
a control feedback circuit configured to generate a replica bias voltage to cause the replica common mode voltage to be substantially the same as the target common mode voltage; and
an output circuit configured to generate the external common mode control current, wherein the external common mode control current is related to the replica bias voltage.

4. The apparatus of claim 3 , wherein the input circuit comprises a variable resistor coupled in series with a current source between the first upper voltage rail and the lower voltage rail, wherein the replica input voltage is generated at a node between the variable resistor and the current source.

5. The apparatus of claim 3 , wherein the replica circuit comprises a replica load device, a replica input transistor, and a replica current source transistor coupled in series between the first upper voltage rail and the lower voltage rail, wherein the replica input transistor includes a gate configured to receive the replica input voltage, and wherein the replica current source transistor includes a gate configured to receive the replica bias voltage.

6. The apparatus of claim 5 , wherein the replica load device comprises a resistor.

7. The apparatus of claim 5 , wherein the replica load device comprises at least one transistor.

8. The apparatus of claim 3 , wherein the target common mode voltage setting circuit comprises a variable resistor coupled in series with a current source between the first upper voltage rail and the lower voltage rail, wherein the target common mode voltage is generated at a node between the variable resistor and the current source.

9. The apparatus of claim 3 , wherein the control feedback circuit comprises:
an operational amplifier configured to generate a voltage related to a difference between the replica common mode voltage and the target common mode voltage;
a first current generating path configured to generate a first current based on the voltage; and
a second current generating path configured to generate a second current based on the first current, wherein the second current generating path is coupled to the first current generating path via a current mirror configuration, and wherein the second current generating path is configured to generate the replica bias voltage.

10. The apparatus of claim 9 , wherein the first current generating path comprises a diode-connected first transistor coupled in series with a second transistor between the first or a second upper voltage rail and the lower voltage rail, wherein the second transistor includes a gate configured to receive the voltage from the operational amplifier.

11. The apparatus of claim 10 , wherein the second current generating path comprises a third transistor coupled in series with a diode-connected fourth transistor between the first or the second upper voltage rail and the lower voltage rail, wherein a gate of the third transistor is coupled to a gate of the diode-connected first transistor, and wherein the diode-connected fourth transistor includes a gate configured to produce the replica bias voltage.

12. The apparatus of claim 11 , wherein the output circuit is configured to generate the external common mode control current based on at least one of the first or second current.

13. The apparatus of claim 12 , wherein the output circuit comprises a fifth transistor coupled in series with a sixth transistor between the first or second upper voltage rail and an output port through which the external common mode control current is supplied to the local common mode voltage control circuit, wherein the fifth transistor includes a gate coupled to the gates of the diode-connected first transistor and the third transistor, and wherein the sixth transistor includes a gate configured to receive an enable signal for selectively outputting the external common mode control current via the output port.

14. The apparatus of claim 11 , further comprising:
a second differential signal processing circuit configured to receive a second input differential signal and generate therefrom a second output differential signal; and
a second local common mode voltage control circuit configured to receive a second external common mode control current and generate therefrom a second bias voltage for gates of third and fourth current source transistors for the second differential signal processing circuit for setting a second common mode voltage of the second output differential signal to substantially the target common mode voltage.

15. The apparatus of claim 14 , wherein the output circuit is configured to:
selectively generate the external common mode control current based on at least one of the first or second current; and
selectively generate the second external common mode control current based on at least one of the first or second current.

16. The apparatus of claim 15 , wherein:
a fifth transistor coupled in series with a sixth transistor between the first or second upper voltage rail and a first output port through which the external common mode control current is supplied to the local common mode voltage control circuit, wherein the fifth transistor includes a gate coupled to the gates of the diode-connected first transistor and the third transistor, and wherein the sixth transistor includes a gate configured to receive a first enable signal for selectively outputting the external common mode control current via the first output port; and
a seventh transistor coupled in series with an eighth transistor between the first or second upper voltage rail and a second output port through which the second external

Assignees

• Qualcomm Inc

Inventors

• Thiagarajan Pradeep
• Yuan Xiaobin
• Rasmus Todd Morgan

Classifications

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03F2203/45488

  the CSC being a pi circuit and a capacitor being used at the place of the resistor · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03G3/001

  Digital control of analog signals · CPC title

• H03F3/4521

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title