Method and apparatus for passive continuous-time linear equalization with continuous-time baseline wander correction

Patent metadata

Field	Value
Publication number	US-2016173299-A1
Application number	US-201414569574-A
Country	US
Kind code	A1
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

First claim

1 . An apparatus comprising:
an amplifier; and an equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

2 . The apparatus of claim 1 , wherein the equalizer is a passive continuous-time linear equalizer.

3 . The apparatus of claim 1 , wherein the BLW corrector is a continuous-time BLW corrector.

4 . The apparatus of claim 1 comprises a reference voltage provider to provide a common mode reference voltage to the amplifier input via the BLW corrector.

5 . The apparatus of claim 1 , wherein the equalizer comprises a high frequency path coupled to an input of a receiver and to the amplifier.

6 . The apparatus of claim 5 , wherein the high frequency path comprises:
a first capacitive device coupled to the input of the receiver and to the amplifier; a second capacitive device; and a resistive device coupled to the amplifier and to the second capacitive device.

7 . The apparatus of claim 6 , wherein the resistive device has programmable resistance.

8 . The apparatus of claim 6 , wherein the second capacitive device has programmable capacitance.

9 . The apparatus of claim 5 , wherein the BLW corrector comprises a low frequency path coupled to the input of the receiver and to the amplifier.

10 . The apparatus of claim 5 , wherein the high frequency path is a differential path.

11 . The apparatus of claim 9 , wherein the low frequency path is a differential path.

12 . The apparatus of claim 9 , wherein the low frequency path comprises one or more resistive devices coupled to the input of the receiver and to the amplifier.

13 . The apparatus of claim 1 , wherein the amplifier is a differential amplifier.

14 . The apparatus of claim 1 further comprises a decision feedback equalizer coupled to an output of the amplifier.

15 . The apparatus of claim 1 further comprises a ground referenced termination impedance coupled to equalizer and the BLW corrector.

16 . An apparatus comprising:
a first pad; a second pad; and a differential equalizer integrated with a differential baseline wander (BLW) corrector coupled to the first and second pads.

17 . The apparatus of claim 16 comprises a reference voltage provider to provide a common mode reference voltage to the differential BLW corrector.

18 . The apparatus of claim 16 comprises an amplifier coupled to the differential equalizer which is integrated with the differential BLW corrector.

19 . The apparatus of claim 16 , wherein the differential equalizer comprises a high frequency path, and wherein the differential BLW corrector comprises a low frequency path.

20 . A system comprising:
a memory; a processor coupled to the memory, the processor having a receiver including:
an amplifier; and
an equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier; and
a wireless interface for allowing the processor to communicate with another device.

21 . The system of claim 20 , wherein the processor comprises a reference voltage provider to provide a common mode reference voltage to the BLW corrector.

22 . The system of claim 20 , wherein the equalizer comprises a high frequency path coupled to an input of a receiver and to the amplifier.

Assignees

• Intel Corp

Inventors

• Islam Syed S
• Ho Yick Yaw
• Swartz Ronald W

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/10

  Compensating for variations in line balance · CPC title

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L25/03254

  Operation with other circuitry for removing intersymbol interference · CPC title