Voltage tolerant circuit and system
US-10879889-B2 · Dec 29, 2020 · US
US11201616B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11201616-B2 |
| Application number | US-202017081888-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 27, 2020 |
| Priority date | Oct 1, 2018 |
| Publication date | Dec 14, 2021 |
| Grant date | Dec 14, 2021 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A voltage tolerant interface circuit includes an input terminal and one or more low-voltage transistors for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal. The voltage tolerant interface circuit also includes a blocking transistor coupled between a control terminal of at least one low-voltage transistor and the input terminal. In some implementations, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the low-voltage transistor. In other implementations, the low-voltage transistor receives a supply voltage higher than the voltage tolerance of the low-voltage transistor. In that implementation, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage is below a predetermined threshold.
Opening claim text (preview).
The invention claimed is: 1. A voltage tolerant interface circuit comprising: an input terminal; at least one low-voltage transistor for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal; a blocking transistor coupled between a control terminal of the at least one low-voltage transistor and the input terminal; wherein the blocking transistor is configured to protect the control terminal of the at least one low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the at least one low-voltage transistor. 2. The voltage tolerant interface circuit of claim 1 , wherein the voltage tolerant interface circuit is configured to compare a voltage applied to a terminal of the blocking transistor to a reference voltage applied to a reference voltage input. 3. The voltage tolerant interface circuit of claim 1 , wherein the blocking transistor is an always-on blocking transistor. 4. The voltage tolerant interface circuit of claim 1 , wherein the voltage tolerance of the at least one low-voltage transistor is up to one volt. 5. The voltage tolerant interface circuit of claim 1 , wherein a voltage tolerance of the blocking transistor is substantially equal to the voltage tolerance of the at least one low-voltage transistor. 6. The voltage tolerant interface circuit of claim 1 , wherein the voltage tolerant interface circuit is included with an integrated voltage regulator as part of a system-on-chip (SoC). 7. A voltage tolerant interface circuit comprising: an input terminal; at least one low-voltage transistor for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal, the at least one low-voltage transistor receiving a supply voltage higher than a voltage tolerance of the at least one low-voltage transistor; a blocking transistor coupled between a control terminal of the at least one low-voltage transistor and the input terminal; wherein the blocking transistor is configured to protect the control terminal of the at least one low-voltage transistor by blocking the voltage received at the input terminal when the voltage is below a predetermined threshold voltage. 8. The voltage tolerant interface circuit of claim 7 , wherein the voltage tolerant interface circuit is configured to compare a voltage applied to a terminal of the blocking transistor to a reference voltage applied to a reference voltage input. 9. The voltage tolerant interface circuit of claim 7 , wherein the blocking transistor is an always-on blocking transistor. 10. The voltage tolerant interface circuit of claim 7 , wherein the voltage tolerance of the at least one low-voltage transistor is up to one volt. 11. The voltage tolerant interface circuit of claim 7 , wherein a voltage tolerance of the blocking transistor is substantially equal to the voltage tolerance of the at least one low-voltage transistor. 12. The voltage tolerant interface circuit of claim 7 , wherein the voltage tolerant interface circuit is included with an integrated voltage regulator as part of a system-on-chip (SoC). 13. A voltage tolerant interface circuit comprising: an input terminal; at least one low-voltage transistor for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal, the at least one low-voltage transistor receiving a supply voltage higher than a voltage tolerance of the at least one low-voltage transistor; a blocking transistor coupled between a control terminal of the at least one low-voltage transistor and the input terminal; wherein the blocking transistor is configured to protect the control terminal of the at least one low-voltage transistor by blocking the voltage received at the input terminal. 14. The voltage tolerant interface circuit of claim 13 , wherein the voltage tolerant interface circuit is configured to compare a voltage applied to a terminal of the blocking transistor to a reference voltage applied to a reference voltage input. 15. The voltage tolerant interface circuit of claim 13 , wherein the blocking transistor is an always-on blocking transistor. 16. The voltage tolerant interface circuit of claim 13 , wherein the voltage tolerance of the at least one low-voltage transistor is up to one volt. 17. The voltage tolerant interface circuit of claim 13 , wherein a voltage tolerance of the blocking transistor is substantially equal to the voltage tolerance of the at least one low-voltage transistor. 18. The voltage tolerant interface circuit of claim 13 , wherein the voltage tolerant interface circuit is included with an integrated voltage regulator as part of a system-on-chip (SoC).
with at least one differential stage · CPC title
the characteristic being amplitude · CPC title
in field-effect transistor switches · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.