Methods and systems for patterning of low aspect ratio stacks

Patent metadata

Field	Value
Publication number	US-10748769-B2
Application number	US-201916407042-A
Country	US
Kind code	B2
Filing date	May 8, 2019
Priority date	May 9, 2018
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

Embodiments of methods and systems for patterning of low aspect ratio stacks are described. In one embodiment, a method may include receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer. The method may also include performing a partial etch of the dielectric layer in a region exposed by the OPL mask. Additionally, the method may include depositing a capping material on a surface of the OPL mask. The method may also include performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth. In such embodiments, the cyclical process generates an output patterned substrate with a target line edge roughness (LER).

First claim

What we claim:

1. A method for patterning of a low aspect ratio stack, comprising:
receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer;
performing a partial etch of the dielectric layer in a region exposed by the OPL mask;
depositing a capping material on a surface of the OPL mask; and
performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth;
wherein the cyclical process generates an output patterned substrate with a target line edge roughness (LER).

2. The method of claim 1 , wherein depositing the capping material on the surface of the OPL mask further comprises depositing a layer of silicon tetrachloride (SiCl 4 ) material.

3. The method of claim 2 , wherein depositing the layer of SiCl 4 comprises performing an in-situ plasma-assisted deposition process.

4. The method of claim 3 , wherein the plasma-assisted deposition process is performed at a chamber pressure in a range of 8 mT or 12 mT.

5. The method of claim 3 , wherein the plasma-assisted deposition process is performed at a source power in a range of 425 W to 575 W.

6. The method of claim 3 , wherein the plasma-assisted deposition process is performed without power applied to a bias source.

7. The method of claim 3 , wherein the plasma-assisted deposition process is performed with SiCl4 gas at a flow rate in a range of 15 sccm to 20 sccm.

8. The method of claim 3 , wherein the plasma-assisted deposition process is performed at a temperature in a range of 15° C. to 25° C.

9. The method of claim 1 , wherein the capping material is deposited primarily on a horizontal surface of a patterned feature in the OPL layer extending from a surface of the dielectric layer.

10. The method of claim 9 , wherein the capping material is deposited primarily on the horizontal surface of the patterned feature in the OPL layer using a material selective deposition process.

11. The method of claim 9 , wherein the capping material is deposited primarily on the horizontal surface of the patterned feature in the OPL layer as a result of the aspect ratio between the horizontal surface of the OPL layer and the depth of the feature formed in the dielectric layer.

12. The method of claim 9 , wherein the quantity of capping material deposited on the horizontal surface of the patterned feature is at least one order of magnitude greater than a quantity of capping material deposited on a surface of the dielectric layer exposed by the patterned OPL layer.

13. The method of claim 1 , wherein the OPL layer has a thickness in a range of 40 nm to 60 nm.

14. The method of claim 1 , wherein the OPL layer has a thickness in a range of 30 nm to 40 nm.

15. The method of claim 1 , wherein the OPL layer is patterned in regions defined by a patterned anti-reflective coating disposed on a surface of the OPL layer.

16. The method of claim 15 , wherein the anti-reflective coating comprises a Silicon Anti-Reflective Coating (SiARC).

17. The method of claim 16 , wherein the SiARC layer has a thickness in a range of 10 nm to 25 nm.

18. The method of claim 1 , performed in conjunction with an Extreme Ultraviolet (EUV) lithography process.

19. The method of claim 1 , wherein a Critical Dimension (CD) of a feature formed in the dielectric layer is in a range of 30 nm to 50 nm.

20. The method of claim 1 , wherein the target line edge roughness (LER) is in a range of 1.5 nm to 2.1 nm.

Assignees

• Tokyo Electron Ltd

Inventors

• Franke Elliott
• Raley Angelique
• Thibaut Sophie

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P72/0421

  for drying etching · CPC title

• H10P50/283

  by chemical means · CPC title