Voltage tolerant circuit and system

Patent metadata

Field	Value
Publication number	US-10879889-B2
Application number	US-201816148232-A
Country	US
Kind code	B2
Filing date	Oct 1, 2018
Priority date	Oct 1, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A voltage tolerant interface circuit includes an input terminal and one or more low-voltage transistors for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal. The voltage tolerant interface circuit also includes a blocking transistor coupled between a control terminal of at least one low-voltage transistor and the input terminal. In some implementations, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the low-voltage transistor. In other implementations, the low-voltage transistor receives a supply voltage higher than the voltage tolerance of the low-voltage transistor. In that implementation, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage is below a predetermined threshold.

First claim

The invention claimed is:

1. A voltage tolerant interface circuit comprising:
an input terminal;
at least one low-voltage transistor for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal;
a blocking transistor coupled between a control terminal of the at least one low-voltage transistor and the input terminal;
wherein the blocking transistor is configured to protect the control terminal of the at least one low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the at least one low-voltage transistor;
wherein the blocking transistor is coupled to the control terminal of the at least one low-voltage transistor by one of an offset-calibration capacitor and a reference capacitor.

2. The voltage tolerant interface circuit of claim 1 , wherein the voltage tolerant interface circuit is configured to compare a voltage applied to a terminal of the blocking transistor to a reference voltage applied to a reference voltage input.

3. The voltage tolerant interface circuit of claim 1 , wherein the blocking transistor is an always-on blocking transistor.

4. The voltage tolerant interface circuit of claim 1 , wherein the voltage tolerance of the at least one low-voltage transistor is up to one volt.

5. The voltage tolerant interface circuit of claim 1 , wherein a voltage tolerance of the blocking transistor is substantially equal to the voltage tolerance of the at least one low-voltage transistor.

6. The voltage tolerant interface circuit of claim 1 , wherein the at least one low-voltage transistor comprises a first low-voltage transistor and a second low-voltage transistor, wherein the control terminal of the at least one low-voltage transistor is a control terminal of the first low-voltage transistor, and wherein a control terminal of the second low-voltage transistor is directly coupled to a reference voltage input.

7. The voltage tolerant interface circuit of claim 1 , wherein the at least one low-voltage transistor comprises a first low-voltage transistor and a second low-voltage transistor, wherein the control terminal of the at least one low-voltage transistor is a control terminal of the first low-voltage transistor, and wherein another blocking transistor is coupled between a control terminal of the second low-voltage transistor and a reference voltage input.

8. The voltage tolerant interface circuit of claim 1 , wherein the voltage tolerant interface circuit is included with an integrated voltage regulator as part of a system-on-chip (SoC).

9. A voltage tolerant interface circuit comprising:
an input terminal;
at least one low-voltage transistor for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal, the at least one low-voltage transistor receiving a supply voltage higher than a voltage tolerance of the at least one low-voltage transistor;
a blocking transistor coupled between a control terminal of the at least one low-voltage transistor and the input terminal;
wherein the blocking transistor is configured to protect the control terminal of the at least one low-voltage transistor by blocking the voltage received at the input terminal when the voltage is below a predetermined threshold voltage;
wherein the blocking transistor is coupled to the control terminal of the at least one low-voltage transistor by one of an offset-calibration capacitor and a reference capacitor.

10. The voltage tolerant interface circuit of claim 9 , wherein the voltage tolerant interface circuit is configured to compare a voltage applied to a terminal of the blocking transistor to a reference voltage applied to a reference voltage input.

11. The voltage tolerant interface circuit of claim 9 , wherein the blocking transistor is an always-on blocking transistor.

12. The voltage tolerant interface circuit of claim 9 , wherein the voltage tolerance of the at least one low-voltage transistor is up to one volt.

13. The voltage tolerant interface circuit of claim 9 , wherein a voltage tolerance of the blocking transistor is substantially equal to the voltage tolerance of the at least one low-voltage transistor.

14. The voltage tolerant interface circuit of claim 9 , wherein the at least one low-voltage transistor comprises a first low-voltage transistor and a second low-voltage transistor, wherein the control terminal of the at least one low-voltage transistor is a control terminal of the first low-voltage transistor, and wherein a control terminal of the second low-voltage transistor is directly coupled to a reference voltage input.

15. The voltage tolerant interface circuit of claim 9 , wherein the at least one low-voltage transistor comprises a first low-voltage transistor and a second low-voltage transistor, wherein the control terminal of the at least one low-voltage transistor is a control terminal of the first low-voltage transistor, and wherein another blocking transistor is coupled between a control terminal of the second low-voltage transistor and a reference voltage input.

16. The voltage tolerant interface circuit of claim 9 , wherein the voltage tolerant interface circuit implements one of an offset-calibrated single-ended comparator and an offset-calibrated differential comparator.

17. The voltage tolerant interface circuit of claim 9 , wherein the voltage tolerant interface circuit is included with an integrated voltage regulator as part of a system-on-chip (SoC).

18. A voltage tolerant interface circuit comprising:
an input terminal;
at least one low-voltage transistor for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal;
a blocking transistor coupled between a control terminal of the at least one low-voltage transistor and the input terminal;
wherein the blocking transistor is configured to protect the control terminal of the at least one low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the at least one low-voltage transistor;
wherein the voltage tolerant interface circuit implements one of an offset-calibrated single-ended comparator and an offset-calibrated differential comparator.

19. The voltage tolerant interface circuit of claim 18 , wherein the voltage tolerant interface circuit is configured to compare a voltage applied to a terminal of the blocking transistor to a reference voltage applied to a reference voltage input.

20. The voltage tolerant interface circuit of claim 18 , wherein the blocking transistor is an always-on blocking transistor.

Assignees

• Empower Semiconductor
• Empower Semiconductor Inc

Inventors

• Oak Parag

Classifications

• H03K5/2481

  with at least one differential stage · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title