Reduced flyback ESD surge protection

Patent metadata

Field	Value
Publication number	US-11201467-B2
Application number	US-201916547762-A
Country	US
Kind code	B2
Filing date	Aug 22, 2019
Priority date	Aug 22, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Reduced flyback electrostatic discharge (ESD) surge protection is disclosed. An ESD protection circuit differentiates ESD events from normal power on based on supply rise time. During an ESD protection cycle, the ESD protection circuit briefly clamps a supply on an identified ESD edge to limit and protect an electronic device from high voltage and/or current. In some cases, a surge condition may occur as the ESD protection circuit becomes disabled, such as in the presence of a fast rise time power supply. When the power supply is also inductive, a flyback voltage overshoot at the sudden release of the ESD clamp can result in permanent over voltage-related device damage. An exemplary ESD protection circuit includes a controlled disable state which reduces or eliminates flyback during such a surge by gradually ramping down current from the ESD protection cycle.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection circuit, comprising:
a supply node;
a ground node;
an ESD clamp coupled between the supply node and the ground node and configured to clamp the supply node when an ESD event is detected;
a driver coupled to the ESD clamp and configured to activate the ESD clamp for a predetermined protection period when the ESD event is detected;
a latch configured to provide an activation signal to cause the driver to activate the ESD clamp; and
a ramp-down driver coupled to the ESD clamp and configured to provide tri-state driving of the ESD protection circuit such that:
in an enable state, the latch and the driver cause the ESD clamp to close;
in a controlled disable state, the ramp-down driver and the driver gradually disable the ESD clamp to reduce a voltage flyback of the supply node; and
in a disable state, the ESD clamp is open.

2. The ESD protection circuit of claim 1 , further comprising a delay circuit coupled to the latch and configured to set the latch, causing the ESD protection circuit to enter the enable state for the predetermined protection period when the ESD event is detected.

3. The ESD protection circuit of claim 2 , wherein after the predetermined protection period, the ESD protection circuit enters the controlled disable state and the ramp-down driver is configured to gradually disable the ESD clamp during a predetermined ramp-down period.

4. The ESD protection circuit of claim 3 , wherein:
the ESD clamp comprises a metal-oxide-semiconductor field-effect transistor (MO SFET);
the ramp-down driver is coupled to a gate of the ESD clamp; and
the predetermined ramp-down period is based on a capacitance of the ESD clamp and a pull-down resistor coupled between the gate of the ESD clamp and the ground node.

5. The ESD protection circuit of claim 2 , wherein the latch is configured to cause the driver to disable the ESD clamp after the predetermined protection period.

6. The ESD protection circuit of claim 5 , wherein the predetermined protection period is provided by a resistor-capacitor (RC) delay.

7. The ESD protection circuit of claim 5 , wherein the predetermined protection period is provided by a series of delay transistors coupled to a capacitor.

8. The ESD protection circuit of claim 1 , wherein the ramp-down driver comprises a NOR gate having a first input coupled to the driver, a second input coupled to a gate of the ESD clamp, and an output coupled to a gate of a transistor coupled between the gate of the ESD clamp and the ground node.

9. The ESD protection circuit of claim 1 , wherein:
the latch is a NAND latch implemented in complementary metal-oxide semiconductor (MOS) (CMOS); and
the driver is implemented in CMOS having a gate of the ESD clamp coupled between a driver P-type MOS (PMOS) transistor and a driver N-type MOS (NMOS) transistor.

10. A method for protecting an integrated circuit (IC) from an electrostatic discharge (ESD) event, comprising:
detecting the ESD event;
causing an ESD protection circuit to enter an enable state by using a NAND-based latch to activate an ESD clamp to clamp a supply voltage in response to detecting the ESD event;
after a predetermined protection period, causing the ESD protection circuit to enter a controlled disable state by gradually releasing the ESD clamp to reduce a flyback in the supply voltage; and
after a predetermined ramp-down period, causing the ESD protection circuit to enter a disable state by opening the ESD clamp.

11. The method of claim 10 , wherein gradually releasing the ESD clamp comprises holding a gate of the ESD clamp in an off condition while controlling current from a voltage source during the predetermined ramp-down period.

12. The method of claim 10 , wherein detecting the ESD event comprises detecting a fast-rising voltage edge of the supply voltage.

13. The method of claim 10 , wherein gradually releasing the ESD clamp dissipates inductance in a voltage source from the predetermined protection period.

14. An electronic device, comprising:
a supply node;
a ground node; and
a first electrostatic discharge (ESD) protection circuit coupled between the supply node and the ground node and comprising:
a first ESD clamp configured to clamp the supply node when an ESD event is detected;
a first driver coupled to the first ESD clamp and configured to activate the first ESD clamp for a predetermined protection period when the ESD event is detected;
a first NAND-based latch configured to provide a first activation signal to cause the first driver to activate the first ESD clamp; and
a first ramp-down driver coupled to the first ESD clamp and configured to gradually disable the first ESD clamp after a predetermined protection period.

15. The electronic device of claim 14 , wherein:
after the predetermined protection period, the first ramp-down driver is configured to gradually disable the first ESD clamp by holding the first ESD clamp off for a predetermined ramp-down period.

16. The electronic device of claim 14 , further comprising a second ESD protection circuit coupled to the first ESD protection circuit and comprising:
a second ESD clamp; and
a second ramp-down driver coupled to the second ESD clamp and configured to gradually disable the second ESD clamp after the predetermined protection period.

17. The electronic device of claim 16 , wherein the second ESD protection circuit is coupled in series with the first ESD protection circuit between the supply node and the ground node.

18. The electronic device of claim 16 , further comprising a diode stack coupled between a gate of the first ESD clamp and a gate of the second ESD clamp.

Assignees

• Qorvo Us Inc

Inventors

• Franck Stephen James

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H02H9/048 Primary

  Anti-latching or quenching devices, i.e. bringing the protection device back to its normal state after a protection action · CPC title