Chip package-in-package

Patent metadata

Field	Value
Publication number	US-2016190107-A1
Application number	US-201615063579-A
Country	US
Kind code	A1
Filing date	Mar 8, 2016
Priority date	Mar 15, 2013
Publication date	Jun 30, 2016
Grant date	—

Abstract

An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.

First claim

What is claimed is:

1 . A chip package, comprising:
a first substrate, wherein the first substrate has a plurality of first substrate electrically conducting vias; a first chip arranged over the first substrate, wherein the first chip is electrically coupled to at least one of the first substrate electrically conducting vias; a second substrate arranged over a side of the first chip facing away from the first substrate, wherein the second substrate has a plurality of second substrate electrically conducting vias; and a first encapsulation material at least partially encapsulating the first substrate, the first chip, and the second substrate, wherein the first encapsulation material has a plurality of first encapsulation electrically conducting vias, wherein at least one of the first encapsulation electrically conducting vias provides an electrical connection from one of the plurality of first substrate electrically conducting vias to one of the plurality of second substrate electrically conducting vias.

2 . The chip package of claim 1 , further comprising a second chip arranged on the second substrate on a side opposite of the first chip, wherein the second chip is electrically coupled to at least one of the second substrate electrically conducting vias.

3 . The chip package of claim 2 , further comprising a second encapsulation material at least partially encapsulating the second chip and the second substrate,
wherein the first encapsulation material further at least partially encapsulates the second chip and the second encapsulation material.

4 . The chip package of claim 2 , wherein the second chip is at least one of the group consisting of ball grid array, land grid array, semi-ball grid array, leadframe, quad flat no leads (QFN), or quad flat package (QFP) package type.

5 . The chip package of claim 2 , wherein the second substrate has an overhanging lateral dimension extending at least in part beyond a lateral dimension of the first chip.

6 . The chip package of claim 2 , wherein the second substrate has an overhanging lateral dimension at least in part beyond a lateral dimension of the second chip.

7 . The chip package of claim 5 , wherein at least one of the first encapsulation electrically conducting vias extends from the overhanging lateral dimension of the second substrate.

8 . The chip package of claim 6 , where at least one of the first encapsulation electrically conducting vias extends from the second substrate on a side opposite of the first chip.

9 . The chip package of claim 8 , wherein at least one of the first encapsulation electrically conducting vias extends from the overhanging lateral dimension of the second substrate.

10 . The chip package of claim 2 , wherein the second chip is an embedded package and is at least one of a pretested and a burned package.

11 . The chip package of claim 2 , further comprising:
a third substrate arranged over the second chip on a side opposite of the second substrate, wherein the third substrate has a plurality of third substrate electrically conducting vias.

12 . The chip package of claim 11 , further comprising:
a third chip arranged over the third substrate on a side opposite of the second chip.

13 . The chip package of claim 11 , wherein the first encapsulation layer further comprises a second series of first encapsulation electrically conducting vias to electrically connect the second substrate to the third substrate.

14 . The chip package of claim 12 , wherein the third chip is electrically coupled to the third substrate.

Assignees

• Intel Deutschland Gmbh

Inventors

• Meyer Thorsten
• Albers Sven
• Wolter Andreas

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title