Semiconductor device package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11201386-B2
Application number	US-201916670487-A
Country	US
Kind code	B2
Filing date	Oct 31, 2019
Priority date	Oct 31, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A semiconductor device package and a method for manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface. The lateral surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a circuit layer having a first surface, a second surface opposite to the first surface;
an antenna module having an antenna pattern layer and disposed on the first surface of the circuit layer;
a metal pillar electrically connected between the antenna pattern layer and the first surface of the circuit layer;
a conductive via electrically connected between the antenna pattern layer and the metal pillar, wherein the conductive via tapers toward the antenna pattern layer; and
an encapsulant covering at least a portion of a lateral surface of the metal pillar;
wherein a passivation layer is disposed between the encapsulant and the antenna pattern layer.

2. The semiconductor device package of claim 1 , wherein the antenna module further comprises a ground layer contacting the first surface of the circuit layer.

3. The semiconductor device package of claim 2 , wherein the ground layer directly contacts the first surface of the circuit layer.

4. The semiconductor device package of claim 2 , wherein the encapsulant is between the ground layer and the antenna pattern layer.

5. The semiconductor device package of claim 1 , wherein the circuit layer further comprises a lateral surface extending between the first surface and the second surface, wherein the lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.

6. The semiconductor device package of claim 1 , wherein the passivation layer comprises a recess.

7. The semiconductor device package of claim 6 , wherein the encapsulant has a surface facing away from the circuit layer and a protruding portion protruded from the surface of the encapsulant that facing away from the circuit layer.

8. The semiconductor device package of claim 6 , wherein the antenna pattern layer is disposed in the recess of the passivation layer.

9. The semiconductor device package of claim 7 , wherein the protruding portion is surrounded by the passivation layer.

10. The semiconductor device package of claim 7 , wherein a width of the protruding portion proximal to the encapsulant is greater than a width of the protruding portion distal from the encapsulant.

11. The semiconductor device package of claim 1 , wherein
the metal pillar has a surface facing the circuit layer;
the encapsulant has a surface facing the circuit layer; and
a portion of the surface of the metal pillar is recessed from the surface of the encapsulant.

12. The semiconductor device package of claim 11 , wherein the portion of the surface of the metal pillar has a curved surface.

13. The semiconductor device package of claim 11 , wherein a gap is defined between the encapsulant and the metal pillar.

14. The semiconductor device package of claim 11 , wherein the encapsulant has a recess from the surface of the encapsulant that facing the circuit layer.

15. The semiconductor device package of claim 13 , wherein the antenna module further comprises a second passivation layer covering the encapsulant and the metal pillar, wherein the second passivation layer is disposed within the gap.

16. The semiconductor device package of claim 15 , wherein the second passivation layer is between the metal pillar and the circuit layer.

17. The semiconductor device package of claim 15 , wherein the second passivation layer has a lateral surface substantially coplanar with a lateral surface of the antenna module.

18. The semiconductor device package of claim 1 , further comprising an electronic component disposed on the second surface of the circuit layer and electrically connected to the antenna module through an interconnection structure within the circuit layer.

19. The semiconductor device package of claim 1 , wherein the passivation layer covers the encapsulant and the metal pillar.

20. A semiconductor device package, comprising:
a circuit layer having a first surface, a second surface opposite to the first surface;
an antenna module having an antenna pattern layer and disposed on the first surface of the circuit layer;
a metal pillar electrically connected between the antenna pattern layer and the first surface of the circuit layer;
an encapsulant covering at least a portion of a lateral surface of the metal pillar, wherein the encapsulant has a surface facing away from the circuit layer and a protruding portion protruded from the surface of the encapsulant; and
a passivation layer disposed between the encapsulant and the antenna pattern layer, wherein the protruding portion is surrounded by the passivation layer.

21. The semiconductor device package of claim 20 , wherein the passivation layer comprises a recess.

22. A semiconductor device package, comprising:
a circuit layer having a first surface, a second surface opposite to the first surface;
an antenna module having an antenna pattern layer and disposed on the first surface of the circuit layer;
a metal pillar electrically connected between the antenna pattern layer and the first surface of the circuit layer; and
an encapsulant covering at least a portion of a lateral surface of the metal pillar, wherein the encapsulant has a surface facing away from the circuit layer and a protruding portion protruded from the surface of the encapsulant;
wherein a width of the protruding portion proximal to the encapsulant is greater than a width of the protruding portion distal from the encapsulant; and
wherein a passivation layer is disposed between the encapsulant and the antenna pattern layer.

23. The semiconductor device package of claim 22 , wherein the passivation layer comprises a recess.

Assignees

• Advanced Semiconductor Eng

Inventors

• Ho Cheng-Lin
• Lee Chih-Cheng
• Chen Chun Chen
• Yu Yuanhao

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title