MOSFET with ultra low drain leakage

Patent metadata

Field	Value
Publication number	US-11201212-B2
Application number	US-201816104411-A
Country	US
Kind code	B2
Filing date	Aug 17, 2018
Priority date	Jul 30, 2015
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

First claim

The invention claimed is:

1. A method for forming a semiconductor, comprising:
etching one or more recesses through a passivation layer on a substrate, and into the substrate, wherein each of the one or more recesses undercut a portion of the passivation layer to form passivation layer overhangs and extend below a portion of a gate conductor on the passivation layer;
depositing a dielectric material on exposed portions of the passivation layer and a bottom surface of at least one of the one or more recesses to form a dielectric pad, wherein there is an exposed portion of the substrate between the dielectric pad and the sidewalls of the recess; and
resizing the gate conductor to expose a portion of the passivation layer.

2. The method as recited in claim 1 , further comprising forming a source/drain region on the dielectric pad in the at least one of the one or more recesses, wherein the source/drain region forms on the exposed portion of the substrate between the dielectric pad and the sidewalls of the recess, wherein the source/drain region is made of a II-VI material.

3. The method as recited in claim 2 , wherein the II-VI material is selected from the group consisting of zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium sulfide (CdS), and cadmium telluride (CdTe).

4. The method as recited in claim 1 , wherein the dielectric material is formed by an evaporation process, and the passivation layer overhangs prevent deposition of the dielectric material on the sidewalls of the recesses.

5. The method as recited in claim 4 , wherein the dielectric material is silicon oxide (SiO).

6. The method as recited in claim 1 , wherein a source/drain region is formed on the dielectric pad in the at least one of the one or more recesses by atomic layer deposition (ALD).

7. The method as recited in claim 6 , wherein the source/drain region includes an amorphous phase.

8. The method as recited in claim 1 , further comprising forming a gate cap on the resized gate conductor.

9. A method for forming a transistor, comprising:
forming a gate conductor on a portion of a passivation layer on a substrate;
etching one or more recesses through the passivation layer and into the substrate, wherein each of the one or more recesses undercut a portion of the passivation layer to form passivation layer overhangs, wherein the at least one of the one or more recesses extends below a portion of the gate conductor;
depositing a dielectric material on exposed portions of the passivation layer and a bottom surface of at least one of the one or more recesses to form a dielectric pad, wherein there is an exposed portion of the substrate between the dielectric pad and the sidewalls of the recess; and
forming a source/drain region on the dielectric pad in the at least one of the one or more recesses, wherein the source/drain region forms on the exposed portion of the substrate between the dielectric pad and the sidewalls of the recess.

10. The method as recited in claim 9 , further comprising resizing the gate conductor to expose a portion of the passivation layer.

11. The method as recited in claim 10 , wherein the source/drain region is made of an n-type material.

12. The method as recited in claim 10 , wherein the source/drain region is made of a non-crystalline material.

13. The method as recited in claim 12 , wherein the source/drain region is selected from the group of materials consisting of zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO).

14. The method as recited in claim 12 , wherein the substrate is a III-V monocrystalline substrate.

15. A method for forming a transistor, comprising:
forming a passivation layer on a substrate, wherein the substrate is a III-V monocrystalline substrate;
etching one or more recesses through the passivation layer into the substrate, wherein each of the one or more recesses undercut a portion of the passivation layer to form passivation layer overhangs, and wherein the at least one of the one or more recesses extends below a portion of a gate conductor;
depositing a dielectric material on exposed portions of the passivation layer and a bottom surface of at least one of the one or more recesses to form a dielectric pad, wherein there is an exposed portion of the substrate between the dielectric pad and the sidewalls of the recess; and
forming a source/drain region on the dielectric pad in the at least one of the one or more recesses, wherein the source/drain region forms on the exposed portion of the substrate between the dielectric pad and the sidewalls of the recess.

16. The method as recited in claim 15 , wherein the substrate is made of indium gallium arsenide (InGaAs) or gallium arsenide (GaAs).

17. The method as recited in claim 16 , wherein the passivation layer is formed by exposing the substrate to activated sulfur.

18. The method as recited in claim 17 , further comprising forming a gate conductor on a portion of the passivation layer.

19. The method as recited in claim 18 , wherein the dielectric material is formed by an evaporation process, and the passivation layer overhangs prevent deposition of the dielectric material on the sidewalls of the recesses.

Assignees

• IBM

Inventors

• De Souza Joel P
• Fogel Keith E
• Kim Jeehwan
• Sadana Devendra K

Classifications

• H10P14/3442

  N-type · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10D64/01358

  the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title