Superconducting nanowire-based programmable processor

Patent metadata

Field	Value
Publication number	US-11200947-B2
Application number	US-201916266507-A
Country	US
Kind code	B2
Filing date	Feb 4, 2019
Priority date	Feb 5, 2018
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Apparatus and methods relating to programmable superconducting cells are described. A programmable superconducting cell can be formed from a superconducting current loop having at least two terminals connected to the loop. The current loop and terminals can be formed from a single layer of superconducting material. The programmable superconducting cell can be incorporated into a crossbar architecture to form a high-speed vector-matrix multiplying processor for deep neural network computations.

First claim

The invention claimed is:

1. A programmable superconducting cell comprising:
a current loop formed from a superconducting material; and
a nanowire constriction formed in the current loop; and
a low-impedance shunt connected to the current loop in parallel with the nanowire constriction;
wherein a resistance value of the low-impedance shunt is between 0.1 ohm and 10 ohms and an inductance value of the low-impedance shunt is between 0.1 picoHenry and 100 picoHenry.

2. The programmable superconducting cell of claim 1 , further comprising:
an input terminal connected to the current loop;
an output terminal connected to the current loop; and
a biasing arm and bias terminal connected to the current loop.

3. The programmable superconducting cell of claim 2 , wherein the biasing arm is formed from the superconducting material and forms a portion of a yTron that is integrated in the current loop.

4. The programmable superconducting cell of claim 3 , wherein a width of the biasing arm is greater than a width of the nanowire constriction.

5. The programmable superconducting cell of claim 3 , further comprising a resistor connected to the bias terminal having a value between 10 ohms and 75 ohms.

6. The programmable superconducting cell of claim 1 , wherein a width of the nanowire constriction is between 10 nm and 200 nm.

7. The programmable superconducting cell of claim 2 configured for multi-level memory.

8. The programmable superconducting cell of claim 2 configured for multiplication and/or division operations.

9. An array of programmable superconducting cells, each programmable superconducting cell comprising:
a current loop formed from a superconducting material;
a nanowire constriction formed in the current loop; and
a low-impedance shunt connected to the current loop in parallel with the nanowire constriction;
wherein a resistance value of the low-impedance shunt is between 0.1 ohm and 10 ohms and an inductance value of the low-impedance shunt is between 0.1 picoHenry and 100 picoHenry.

10. The array of claim 9 , configured for multi-level memory storage.

11. The array of claim 9 , configured for vector-matrix multiplication.

12. The array of claim 9 , configured in a crossbar architecture for deep neural network computation.

13. The array of claim 9 , wherein each programmable superconducting cell further comprises:
an input terminal connected to the current loop;
an output terminal connected to the current loop; and
a biasing arm, resistor, and bias terminal connected to the current loop.

14. The array of claim 13 , further comprising:
first lines connecting the input terminals in first rows;
second lines connecting the output terminals in columns; and
third lines connecting the bias terminals in second rows.

15. The array of claim 14 , wherein the second lines and third lines are configured as input/output lines.

16. A method of programming a memory state of a programmable superconducting cell, the method comprising applying at least one pulse of energy to the superconducting cell that causes a nanowire constriction in a superconducting loop to transition from a superconducting state to a normal resistive state;
wherein the at least one pulse comprises two electrical pulses that are timed to arrive at the constriction concurrently, such that the sum of energy from the two pulses causes the nanowire constriction to transition from the superconducting state to the normal resistive state whereas energy from one of the two pulses does not cause the nanowire constriction to transition from the superconducting state to the normal resistive state.

17. The method of claim 16 , wherein the energy of the at least one pulse is selected to cause a single flux quantum transition from a first memory state of the programmable superconducting cell to a second memory state of the programmable superconducting cell that is adjacent in energy to the first memory state.

18. The method of claim 17 , further comprising applying at least one additional pulse that causes a single flux quantum transition from the second memory state of the programmable superconducting cell to a third memory state of the programmable superconducting cell that is adjacent in energy to the second memory state and different from the first memory state.

19. The method of claim 16 , wherein the at least one pulse is an optical pulse applied to the nanowire constriction.

20. The method of claim 16 , wherein the energy of the at least one pulse is selected to cause a multi-flux quantum transition from a first memory state of the programmable superconducting cell to a second memory state of the programmable superconducting cell.

21. A method of multiplying or dividing with a programmable superconducting cell, the method comprising:
applying a current ramp to a biasing terminal that is coupled to a superconducting current loop, having a nanowire constriction formed therein, of the programmable superconducting cell; and
integrating an amount of current output from an output terminal coupled to the superconducting current loop;
wherein a low-impedance shunt connected to the current loop in parallel with the nanowire constriction; and
wherein a resistance value of the low-impedance shunt is between 0.1 ohm and 10 ohms and an inductance value of the low-impedance shunt is between 0.1 picoHenry and 100 picoHenry.

22. The method of claim 21 , further comprising programming an amount of current circulating in the superconducting current loop.

23. The method of claim 22 , wherein the programming comprises causing the nanowire constriction formed in the current loop to transition from a superconducting state to a normal resistive state.

24. A method of performing deep neural network calculations with an array of programmable superconducting cells, the method comprising:
performing a forward-pass multiplication of a vector times a matrix wherein vector inputs are provided as current ramps applied to biasing arms that are connected in rows to superconducting current loops in the programmable superconducting cells and matrix values are stored as circulating currents in the superconducting current loops; and
integrating output currents from output terminals connected in columns to the superconducting current loops.

25. The method of claim 24 , further comprising:
performing a backward-pass multiplication of the vector time a transpose of the matrix wherein the vector inputs are provided as inverted current ramps applied to the output terminals and the matrix values are unchanged in the superconducting current loops; and
integrating output currents from the biasing terminals.

26. A method of making a programmable superconducting cell, the method comprising:
forming a current loop from a superconducting material on a substrate;
forming a nanowire constriction in the current loop; and
forming a low-impedance shunt connected to the current loop in parallel with the nanowire constriction;
wherein a resistance value of the low-impedance shunt is between 0.1 ohm and 10 ohms and an inductance value of the low-impedance shunt is between 0.1 picoHenry and 100 picoHenry.

27. The method of claim 26 , further comprising:
forming an input terminal connected to the current loop;
forming a biasing terminal connected to the current loop; and
forming an output terminal connected to the current loop.

Assignees

• Massachusetts Inst Technology

Inventors

• Berggren Karl K
• Onen Oguzhan Murat
• Butters Brenden
• Toomey Emily

Classifications

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title